Dynamic memory buffer allocation method and system

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711S170000

Reexamination Certificate

active

08032675

ABSTRACT:
A method, computer program product, system (including a circuit card), and integrated circuit for initializing a buffer pool, such that the buffer pool includes a plurality of data buffers available for use during a plurality of I/O transfers. In response to the initiation of a first I/O transfer concerning a first data portion being transferred from a first data source to a first data target, the first data portion is written to a first portion of the plurality of data buffers. The first data portion is transferred to the first data target, and the first portion of the plurality of data buffers is released back to the buffer pool for use during one or more subsequent I/O transfers.

REFERENCES:
patent: 4603382 (1986-07-01), Cole et al.
patent: 5379412 (1995-01-01), Eastridge et al.
patent: 5561785 (1996-10-01), Blandy et al.
patent: 5682553 (1997-10-01), Osborne
patent: 5687392 (1997-11-01), Radko
patent: 5784698 (1998-07-01), Brady et al.
patent: 5983289 (1999-11-01), Ishikawa et al.
patent: 6263337 (2001-07-01), Fayyad et al.
patent: 6549982 (2003-04-01), Yamanaka
patent: 7299269 (2007-11-01), Elving
patent: 7451254 (2008-11-01), Peterson et al.
patent: 2004/0141650 (2004-07-01), Hansson et al.
patent: 2007/0074221 (2007-03-01), Stenson et al.
Serial ATA II: Extensions to Serial ATA 1.0a Revision 1.2 ; Aug. 27, 2004, 110 pgs.
“American National Standard for Information Technology—Fibre Channel—Physical and Signalling Interface-3 (FC-PH-3)”,Developed by incits, Where IT all Begins, Table of Contents, (1998), 6 pgs.
“PCI Express Base Specification Revision 1.0”,PCI Express, Table of Contents, (Jul. 22, 2002), 15 pgs.
“PCI-X Addendum to the PCI Local Bus Specification”,Revision 1.0a, Table of Contents, (Jul. 24, 2000), 9 pgs.
“Serial ATA: High Speed Serialized AT Attachment, Serial ATA Workgroup”,Revision 1.0a, Table of Contents, APT Technologies, Inc., (Jan. 7, 2003), 10 pgs.
“Working Draft American National Standard, Project T10/1601-D”,Revision 1, Table of Contents, Information Technology—Serial Attached SCSI-1.1 (SAS-1.1),(Sep. 18, 2003), 24 pgs.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Dynamic memory buffer allocation method and system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic memory buffer allocation method and system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic memory buffer allocation method and system will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4278724

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.