Dynamic memory array with segmented bit lines

Details Dynamic memory array with segmented bit lines Dynamic memory array with segmented bit lines

1984-07-26

1987-04-14

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Capacitors

365154, 365230, G11C 1140

Patent

active

046583777

ABSTRACT:
A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells, with a differential sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects a segment to be connected to the bit line. The ratio of storage capacitance to effective bit line capacitance is increased, because the bit line itself is of lower capacitance to the substrate.

REFERENCES:
patent: 4397002 (1983-08-01), Brosch et al.
patent: 4419743 (1983-12-01), Taguchi et al.

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