Static information storage and retrieval – Read/write circuit – For complementary information
Reexamination Certificate
1999-08-11
2001-04-03
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
For complementary information
C365S230030, C365S189011
Reexamination Certificate
active
06212109
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, and particularly to architecture and organization of a dynamic random-access memory array and associated supporting circuitry for its high-speed writing.
2. Description of Related Art
Semiconductor random-access memory devices or sub-systems using arrays of dynamic memory cells (e.g., 1-transistor/1-capacitor (IT/1C) cells) have consistently provided greater density and lower cost per bit than those using static memory cells (e.g., 6-transistor (6T) cells, or 4-transistor/2-resistor (4T/2R) cells). However, such dynamic random-access memory arrays have historically also been lower in performance when compared to static random-access memory arrays. Consequently, system designers have typically chosen dynamic memory arrays (e.g., commercially available dynamic random access memories, or DRAMs) when high density and low cost are required, such as for CPU main memory applications. Conversely, designers have typically chosen static memory arrays when the highest possible performance is required, such as for cache memory and high speed buffer applications. Examples of static memory array devices or sub-systems include commercially available static random access memories (SRAMs) and CPU-resident on-board cache memory sub-systems.
The reasons often cited for the lower performance of dynamic memory arrays include the destructive sensing of all memory cells common to the addressed word line (encountered in virtually all dynamic memory arrays) and the consequential need to restore data back into each sensed memory cell during the active cycle, the need to equilibrate bit lines and various other differential nodes and to precharge various circuit nodes between active cycles, and the requirement for periodic refreshing of all dynamic memory cells.
The need for ever-increasing memory performance at reasonable cost continues unabated. It is being driven by numerous advances toward higher frequency and higher speed applications. For example, the increasing bandwidth demands of computer networking and the internet, the increasing speeds of commercially available processors, and the proliferation of high-frequency wireless communication systems are all driving the need for higher performance memory sub-systems.
In spite of the performance gains of the last 20 years, there is an unfilled need for higher performance dynamic memory arrays which leverages the lower cost-per-bit usually associated with dynamic memory arrays into the performance realm and ease of use usually associated with static memory arrays.
SUMMARY OF THE INVENTION
The present invention enhances the performance of dynamic memory arrays by providing for internal write operations which proceed, for many embodiments, at the same speed as internal read operations by “fooling” a bit line sense amplifier and letting it actually restore the voltage levels onto the bit lines in accordance with the data to be written, rather than in accordance with the data previously stored in a selected memory cell. Consequently, such a write cycle may be designed to take the same very short time as a read cycle, rather than the longer time typically required to first sense old data, then modify it with the data to be written. In addition, a significant amount of power may be saved, for example, by not having to over-power many sense amplifiers after they have already been latched.
In one embodiment of the present invention useful for an integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, the integrated circuit includes: (1) a first array block including a first plurality of true and complement bit line pairs; (2) a first plurality of bit line sense amplifiers, each coupled to a respective one of the first plurality of bit line pairs, and each responsive to a sense amplifier enable signal; (3) a first complementary pair of local bus lines associated with the first plurality of bit line sense amplifiers; (4) a first plurality of coupling circuits, each associated with a respective one of the first plurality of bit line sense amplifiers, each arranged to receive a differential write data signal on the first complementary pair of local bus lines and, when selected for writing, to communicate a corresponding differential write signal to the respective one of the first plurality of bit line sense amplifiers prior to latching the first plurality of bit line sense amplifiers; (5) a first complementary pair of global input bus lines associated with the first plurality of bit line pairs and further associated with a respective plurality of bit line pairs located within respective array blocks other than the first array block; (6) a second coupling circuit arranged to receive a differential write data signal on the first complementary pair of global input bus lines and to communicate the differential write data signal to the first complementary pair of local bus lines; and (7) a sense amplifier enable control circuit for generating the sense amplifier enable signal for the first plurality of bit line sense amplifiers at a time during a memory cycle substantially irrespective of whether the memory cycle is a read cycle or a write cycle.
In another embodiment of the present invention useful for an integrated circuit including a dynamic memory array of individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, the integrated circuit includes: (1) a first array block including a first plurality of true and complement bit line pairs; (2) a first plurality of bit line sense amplifiers, each coupled to a respective one of the first plurality of bit line pairs, and each responsive to a sense amplifier enable signal; (3) a first complementary pair of bus lines associated with the first plurality of bit line pairs; (4) a first plurality of coupling circuits, each associated with a respective one of the first plurality of bit line sense amplifiers, each arranged to receive a differential write data signal on the first complementary pair of bus lines and, when selected for writing, to communicate, prior to latching the first plurality of bit line sense amplifiers, a corresponding differential write signal to the respective one of the first plurality of bit line sense amplifiers, which corresponding write signal substantially swallows a respective read signal otherwise developed as a result of accessing a respective memory cell; and (5) a sense amplifier enable control circuit for generating the sense amplifier enable signal for the first plurality of bit line sense amplifiers.
In yet another embodiment of the present invention useful for an integrated circuit including a dynamic memory array of individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, the integrated circuit includes: (1) a first array block including a first plurality of true and complement bit line pairs; (2) a first plurality of bit line sense amplifiers, each coupled to a respective one of the first plurality of bit line pairs, and each responsive to a sense amplifier enable signal; (3) a first complementary pair of bus lines associated with the
Integrated Device Technology Inc.
Le Vu A.
Zagorin O'Brien & Graham LLP
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