Dynamic memory

Static information storage and retrieval – Read/write circuit – Differential sensing

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Details

365149, 365189, 365154, G11C 1300, G11C 1140

Patent

active

046513060

ABSTRACT:
When half-size dummy cells are used in a dynamic memory, it is difficult to increase the relative accuracy of the capacitors in the half-size dummy cells and the capacitors in memory cells. According to the present invention, a pair of full-size dummy cells is provided connected to a pair of bit lines. High-level and low-level signals amplified by the sense amplifier are written into the full-size dummy cells, the capacitors of the pair of full-size dummy cells are then short-circuited by a short-circuiting circuit, and the electric charges in the capacitors provide a reference level. This method does not need a generator circuit providing a voltage of 1/2 V.sub.CC (V.sub.CC : power-source voltage) which would necessitate a large quantity of power to drive it.

REFERENCES:
patent: 4493056 (1985-01-01), Mao
patent: 4547868 (1985-10-01), Childers et al.
"Sense Amplifier Design is Key to 1-Transistor Cell in 4,096-Bit Ram" Kuo et al., Electronics, Sep. 1973, pp. 116-121.
1972 IEEE International Solid-State Circuits Conference "Digest of Technical Papers", Feb. 1972, Storage Array and Sense/Refresh Circuit for Single-Transistor Memory Cells, K. U. Stein et al., pp. 56-57.
IEEE Journal of Solid-State Circuits, vol. SC15, No. 5, Oct. 1980, "A 100 ns 5 V Only 64K1 MOS Dynamic RAM" Chan et al., pp. 839-846.

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