Dynamic memory

Details Dynamic memory Dynamic memory

1995-09-08

1997-07-29

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Differential sensing

365149, G11C 700

Patent

active

056527284

ABSTRACT:
Dummy information of a third level, which is between first and second levels written in a plurality of memory cells, is written in a dummy memory cell from a source node through transistors. Thus, a potential difference is caused between a read bit line and a dummy read bit line in reading. A potential comparison circuit indicates the level of information read from any memory cell on the basis of the comparison result as to the potentials of the dummy read bit line and the read bit line. Thus, the read rate is increased, the read operation is stabilized and increase of the chip area is suppressed.

REFERENCES:
patent: 4491858 (1985-01-01), Kawamoto
patent: 4803664 (1989-02-01), Itoh
patent: 4935896 (1990-06-01), Matsumura et al.
"A 3V, 100Mhz, 35wW, Dynamic Line Memory Marco Cell for HDTV Applications" IEEE 1992 Custom Integrated Circuits Conference.
"An Experimental 2-bit/Cell Storage DRAM for Macrocell or Memory-on-Logic Application" IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989.

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