Dynamic memory

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

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Details

365206, 365210, 365203, G11C 700, G11C 1140

Patent

active

049072005

ABSTRACT:
A dynamic memory having pairs of bit lines. A sense amplifier is connected between each pair of bit lines for detecting data from the potential difference between these bit lines. The memory further comprises first and second pair of dummy word lines. A capacitor is coupled between the first of each pair of bit lines, on the one hand, and the first pair of dummy word lines, on the other. Similarly, a capacitor is coupled between the second of each pair of bit lines, on the one hand, and the second pair of dummy word lines, on the other. A first dummy word line driver is connected to the first pair of dummy word lines, for generating a reference potential in the first of each pair of bit lines. A second dummy word line driver is connected to the second pair of dummy word lines, for generating a reference potential in the second of each pair of bit lines. The memory also has a selection circuit for selecting either the first or second dummy word line driver. During a precharging period, either dummy word line driver sets both pairs of dummy word lines at a precharging potential. During a data-reading period, the dummy word line driver selected by the selection circuit sets the dummy word lines at a high potential and a low potential, respectively, and the dummy word line driver selected by the selection circuit sets both dummy word lines at a precharging potential.

REFERENCES:
patent: 4409679 (1983-10-01), Kurafuji et al.
patent: 4740926 (1988-04-01), Takemae et al.
"A 1 Mb CMOS DRAM with Fast Page and Static Column Modes", 1985 IEEE International Solid-State Circuits Conference, Session XVII Megabit DRAMs, Feb. 15, 1985, Saito et al., pp. 252-253.

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