Abrading – Precision device or process - or with condition responsive... – With indicating
Reexamination Certificate
2001-07-11
2004-06-08
Eley, Timothy V. (Department: 3724)
Abrading
Precision device or process - or with condition responsive...
With indicating
C451S041000, C451S054000, C451S057000, C451S059000, C451S063000
Reexamination Certificate
active
06746308
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to the field of semiconductor manufacturing, and, more particularly, to dynamic lot allocation based upon wafer state characteristics, and a system for accomplishing same.
2. Description of the Related Art
Modern integrated circuit devices are comprised of millions of devices, e.g., transistors, formed above a semiconductor wafer comprised of, for example, silicon. Typically, integrated circuit devices are formed above a substrate in the shape of a flat, cylindrical wafer. Current semiconductor manufacturing operations use 8-inch diameter wafers. However, it is anticipated that 12-inch diameter wafers will be used in the immediate future. Additional increases in wafer size may also occur in the more distant future.
In general, the process of forming integrated circuits involves the formation of layers or films of material, selective removal of portions of those layers, introducing dopant atoms into the substrate at predefined locations, and formation of a plurality of conductive interconnections that will allow the devices to electrically communicate with one another and perform their intended function. The processes involved include, for example, deposition processes, etching processes, ion implantation processes, photolithography processes, thermal growth processes and various heat treating processes. The processes may be performed in a variety of process flows or sequences to form completed integrated circuit devices. Given the very small feature sizes on modern integrated circuit devices, e.g., 0.18 &mgr;m and less, great care is taken in performing each and every processing step, e.g., deposition, etch, polish, etc., in an effort to achieve the precision required to form the small features on modern integrated circuit devices.
Nevertheless, despite efforts to the contrary, processed wafers may exhibit variations in one or more characteristics or states. For example, with reference to
FIG. 1
, when a process layer
12
, e.g., silicon dioxide, is formed above a wafer
10
and thereafter subjected to a chemical mechanical polishing process, a surface
14
of the process layer
12
may be domed as a result of a so-called edge-fast (or center-slow) polishing process (the view depicted in
FIG. 1
is exaggerated for purposes of explanation). Alternatively, although not depicted in
FIG. 1
, the surface
14
of the process layer
12
may be dished as a result of a center-fast (or edge-slow) polishing process. By way of another example, as depicted in
FIG. 2
, due to a variety of factors, gate electrodes
16
formed above different regions of a wafer
10
may exhibit significantly different critical dimensions
15
. For example, as depicted in
FIG. 2
, the gate electrodes
16
near an edge region
18
have a larger critical dimension
15
as compared to the critical dimension
15
of gate electrodes
16
near a center region
20
of the wafer
10
. As another example, in photolithography operations, a layer of photoresist may be formed such that the thickness of the layer of photoresist is greater at the edge of the wafer
10
as compared to the center of the wafer
10
.
All of these variations can have an adverse impact on subsequent processing, device yields and overall manufacturing efficiencies. For example, if a process layer is formed too thick in a given region, this over-thickness may determine the minimum required etch time for the entire layer, as complete removal of the etched portions of the process layer must be assured. As a result, the additional etch time required to etch through the additional thickness of the process layer may damage the underlying process layers, and/or cause difficulty in maintaining feature size accuracy in other areas of the process layer. As another example, forming a layer of photoresist above a process layer that has a domed or dished surface profile may result in the layer of photoresist having areas of differing thickness. As a result, subsequent exposure processes performed in a stepper tool may be adversely impacted. For example, given the variation in photoresist thickness, there may be unacceptable deviations in the critical dimension of photoresist features formed in areas of the layer of photoresist having different thicknesses.
Efforts have been made to adjust various process parameters based upon wafer characteristic variations. For example, as shown in
FIG. 1
, if it is determined that, as a result of a polishing process, a process layer
12
has a domed surface
14
, a subsequent layer
17
(indicated by dashed lines) formed above the domed layer
12
may be formed using a deposition process that is designed or modified to deposit more material on the edge region
18
of the wafer
10
than in the center region
20
of the wafer
10
. Other modifications may be made to other processes in an effort to compensate for such variations in wafer characteristics. However, all of these methodologies generally involve varying one or more parameters of a processing operation on a lot-by-lot or wafer-by-wafer basis. Such methodologies may, in some cases, require extensive capital, material and labor to implement, and they may not be necessary or appropriate for some semiconductor manufacturing operations.
The present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
In one illustrative embodiment, the method comprises providing a plurality of wafer lots, each of the lots comprising a plurality of wafers, performing at least one process operation on at least some of the wafers in each of the plurality of lots, identifying processed wafers having similar characteristics, re-allocating the wafers to lots based upon the identified characteristics, and performing additional processing operations on the identified wafers having similar characteristics in the re-allocated lots. In a further embodiment, the method involves identifying wafers having similar across-wafer characteristics and re-allocating the lots of wafers on that basis.
In another illustrative embodiment, the present invention is directed to a system comprised of a first processing tool for performing processing operations on each of a plurality of wafers in each of a plurality of wafer lots, a controller for identifying processed wafers having similar characteristics and re-allocating the wafers to lots based upon the identified characteristics, and a second processing tool adapted to perform additional processing operations on the identified wafers having similar characteristics in the re-allocated lot.
REFERENCES:
patent: 6062954 (2000-05-01), Izumi
patent: 6213847 (2001-04-01), Torii
patent: 6309279 (2001-10-01), Bowman et al.
patent: 6338668 (2002-01-01), Lin et al.
patent: 6354922 (2002-03-01), Sakurai et al.
patent: 6431964 (2002-08-01), Ishikawa et al.
patent: 6517412 (2003-02-01), Lee et al.
patent: 6524163 (2003-02-01), Stirton
patent: 6565416 (2003-05-01), Dunton et al.
Bode Christopher A.
Pasadyn Alexander J.
Eley Timothy V.
Williams Morgan & Amerson P.C.
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