Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2007-02-06
2007-02-06
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S095000, C327S201000
Reexamination Certificate
active
10730168
ABSTRACT:
A dynamic logic return-to-zero (RTZ) latching mechanism including a complementary pair of evaluation devices responsive to a clock signal, a dynamic evaluator, delayed inversion logic, and latching logic. The dynamic evaluator is coupled between the complementary pair of evaluation devices at a pre-charged node and evaluates a logic function based on at least one input data signal. The latching logic asserts the logic state of an output node based on the state of the pre-charged node during an evaluation period between an operative edge of the clock signal and the next edge of an evaluation complete signal, which is a delayed and inverted version of the clock signal. The output node is returned to zero between evaluation periods. A footless latching domino circuit may be added to convert the RTZ output to a registered output signal.
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Partovi H et al: “Flow-through latch and edge-triggered flip-flop hybrid elements” Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE Internatioanl San Francisco, CA, USA Feb. 8-10, 1996, New York, NY, USA, IEEE, US, Feb. 8, 1996, pp. 138-139, XP010156427 ISBN: 0-7803-3136-2 *figure 8*.
Cho James H.
Huffman James W.
Huffman Richard K.
IP-First LLC
Stanford Gary R.
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