Dynamic logic interconnect speed-up circuit

Details Dynamic logic interconnect speed-up circuit Dynamic logic interconnect speed-up circuit

1993-10-22

1995-08-08

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 17, 326 45, 326 83, 327 76, H03K 1901

Patent

active

054401828

ABSTRACT:
A circuit style, which may be employed in fast, area-efficient, flexible programmable interconnect architectures, is disclosed. In one embodiment, a plurality of clocked dynamic logic circuits, each having a single network node, is connected to the intermediate nodes of a programmable interconnect architecture. During the precharge clock phase, the circuits precharge the intermediate nodes to a high logic level. During the evaluation clock phase, each circuit is initially in the stand-by state, in which it monitors the logic level on its network node. If a substantial deviation from the high level towards the low level is detected, the circuit switches to the discharge state, in which it enforces that level change by connecting its network node to the low level. This causes the potential on neighboring nodes, connected through conducting programmable switches, to change towards a low level, and their circuits in turn switch to the discharge state. Thus, a forced high-to-low level change on a node during the evaluation clock phase quickly propagates to its connected nodes.

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