Dynamic logic having power-down mode with periodic clock refresh

Details Dynamic logic having power-down mode with periodic clock refresh Dynamic logic having power-down mode with periodic clock refresh

1995-09-25

1996-12-24

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 97, 327198, 327200, H03K 1900, H03K 19096

Patent

active

055876722

ABSTRACT:
A controller chip has dynamic logic which is driven by a suspendable clock. Power is reduced in a standby mode when the clock to the dynamic logic is stopped. However, power is still applied to the dynamic logic in standby mode so that the dynamic logic can be quickly resumed without the delay of re-charging the power-supply capacitances in the dynamic logic. Stopping the clock to dynamic logic can eventually cause loss of data. A more severe problem than data loss is power consumption. When the clock is stopped to dynamic logic, the isolated nodes leak and eventually their voltages change. When their voltages change by more than a transistor threshold voltage then both the p-channel and n-channel transistors in dynamic logic cells can turn on, forming a direct current paths between power and ground. Thus power consumption can increase dramatically in suspend mode. The isolated dynamic nodes of the dynamic logic are instead recharged periodically during suspend mode. A timer triggers generation of intermittent clock pulses which are applied to the clock to the dynamic logic, recharging the isolated nodes. When data loss can be tolerated, the intermittent pulses ensure that power consumption does not jump due to the voltage changes on the isolated dynamic nodes.

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