Dynamic logic gate with relaxed timing requirements and output s

Details Dynamic logic gate with relaxed timing requirements and output s Dynamic logic gate with relaxed timing requirements and output s

1997-10-22

2000-06-13

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326121, H03K 19096

Patent

active

060753862

ABSTRACT:
A dynamic logic gate having a short precharge period during an evaluation phase of a clock and a tri-state hold period during a precharge phase of the clock. The evaluation time is extended into the precharge phase. As a result of extended evaluation time and no latching set-up time, evaluation timing for upstream logic is relaxed since upstream logic is not required to evaluate before the worst case time for the clock to enter the precharge phase. The gate provides the function of latching without the delay of latching. As a result of holding during the precharge phase of the clock, one latch is eliminated for testing. As a result of tri-stating during the precharge phase of the clock, control during testing is simplified. In a single-rail embodiment, the short precharge period is open loop. In a dual-rail implementation, the precharge period ends when both evaluation nodes are charged. In the dual-rail implementation, both evaluate nodes are tri-stated as soon as one node discharges, thereby providing first incidence latching.

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