Dynamic logic circuits with reduced evaluation time

Details Dynamic logic circuits with reduced evaluation time Dynamic logic circuits with reduced evaluation time

1999-09-08

2001-09-04

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C326S093000, C327S051000

Reexamination Certificate

active

06285217

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to dynamic logic gates, and more particularly to logic gates with short evaluation times.
2. Description of Related Art
Dynamic logic circuits are well known in the art. Dynamic Random Access Memory (RAM) arrays use dynamic logic to decrease device count, and microprocessors use dynamic logic to decrease device count and increase speed. Referred to as domino circuits, clocked dynamic logic performs evaluation and storage functions in VLSI (Very Large Scale Integration) designs and is a preferred topology in microprocessors and memory devices designed for high speed operation.
In order to achieve high speed in dynamic logic circuits, control signals are used to precharge nodes in the circuits to known values, typically at or near one of the power supply rails. There is typically a precharge state and then an evaluation state in which the logic evaluation takes place.
Several domino circuit families are in widespread use today. These can include footed types, where the logic ladders are disconnected from one rail during the precharge phase, or unfooted designs. They can also be single rail or dual rail. Dual rail designs use differential ladders and provide complementary outputs. Another topology is the pseudo-clocked topology, where one of the logic inputs is used to control the evaluation state.
In a logic gate, evaluation of the AND-OR logical product-sum function is typically provided by ladders of input transistors, where serial connection of transistor sources and drains provide an AND function. By way of example, referring to
FIG. 1
, NFETS QF
4
, QF
5
and QF
6
form one such input ladder. Unless all of these devices are on, the ladder does not lower the voltage at node n1. Parallel connection of these AND ladders provides the OR function. NFETS QF
3
, QF
12
and QF
13
provide a second AND ladder. Both of these ladders must be inactive for the voltage at node n1 to remain precharged during an evaluation cycle, therefore the parallel combination accomplishes an OR function. As more OR terms are added, more parallel switching ladders add capacitive loading to the evaluation node. As more AND terms are added, the transistor areas have to be increased to maintain the same resistive path to the rail. Footing transistors such as QF
11
likewise have to be increased in size as more AND terms are added. If the resistive path increases, the evaluation speed of the gate will suffer and the switching ability of the AND ladder will be reduced due to higher voltage at the node at the top of the AND ladder. Again referring to
FIG. 1
, by way of example, device QF
6
has a higher turn on threshold than QF
4
, since the voltage at the source of QF
6
is higher by the potential across QF
4
and QF
5
. This affects the switching speed at input a, which sets a practical limitation on the number of AND terms which can be obtained in a ladder for a fixed transistor area. Increasing the area of the transistors also increases the capacitive loading at the evaluation node. This capacitive loading increases the evaluation time of the dynamic logic gate.
It would, therefore, be desirable to provide a dynamic logic circuit with reduced evaluation time, so that more AND and OR terms can be added to a gate for a desired evaluation speed.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide a logic circuit with reduced evaluation time.
It is therefore another object of the present invention to provide a logic circuit with reduced evaluation time that provides a means for increasing the rate of change of the voltage at the output of a logic input ladder.
It is yet another object of the present invention to provide a logic circuit that includes a cross-coupled amplifier to increase the rate of change of a voltage at an output node of a logic input ladder.
The foregoing objects are achieved in an enhanced dynamic logic circuit that includes a means for increasing the rate of change of the voltage at the output of the logic input ladder by connecting a cross-coupled amplifier to the output of the input ladder and precharging both the amplifier and output nodes of the input ladder during the precharge state. The cross-coupled amplifier increases the rate of change of the voltage at the output of the logic input ladder to reduce evaluation time.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 5543735 (1996-08-01), Lo
patent: 5757205 (1998-05-01), Ciraula et al.
patent: 5920218 (1999-07-01), Klass et al.
patent: 5986475 (1999-11-01), Kim et al.
patent: 6118304 (2000-09-01), Potter et al.
patent: 6127853 (2000-10-01), Yu
patent: 6137319 (2000-10-01), Krishnamurthy et al.
patent: 6147514 (2000-11-01), Shiratake

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