Dynamic logic circuits using transistors having differing thresh

Details Dynamic logic circuits using transistors having differing thresh Dynamic logic circuits using transistors having differing thresh

1996-07-19

1998-11-03

Yoo, Do Hyun

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 95, 326 98, H03K 19096

Patent

active

058314512

ABSTRACT:
In a preferred logic circuit embodiment (10), there is a precharge node (14) coupled to be precharged to a precharge voltage (V.sub.DD) during a precharge phase and operable to be discharged during an evaluate phase. The circuit also includes a conditional series discharge path (22, 24, and 16) connected to the precharge node and operable to couple the precharge node to a voltage different than the precharge voltage. The conditional series discharge path includes a low threshold voltage transistor (22 or 24) having a first threshold voltage, and a high threshold voltage transistor (16) having a second threshold voltage higher in magnitude than the first threshold voltage, wherein a voltage connected to a gate of the high threshold voltage transistor is disabling during the precharge phase.

REFERENCES:
patent: 5440243 (1995-08-01), Lyon
patent: 5459693 (1995-10-01), Komarek et al.
patent: 5483181 (1996-01-01), D'Souza
patent: 5541885 (1996-07-01), Takashima
patent: 5602497 (1997-02-01), Thomas

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