Dynamic logic circuit with reduced charge leakage

Details Dynamic logic circuit with reduced charge leakage Dynamic logic circuit with reduced charge leakage

1994-12-16

1996-01-09

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 95, 326171, H03K 19096

Patent

active

054831814

ABSTRACT:
A dynamic logic circuit with reduced charge leakage includes a dynamic complementary MOSFET logic circuit with a P-type MOSFET, a number of N-type MOSFETs and a static CMOSFET inverter circuit. In response to a low clock signal, the P-type MOSFET turns on and charges the precharge node to a precharged node voltage. Some of the N-type MOSFETs are interconnected to form a logic circuit to logically process incoming logic signals and in accordance therewith selectively provide a conduction path for electrical charges from the precharge node. In response to a high clock signal, another N-type MOSFET turns on and together with the logic circuit conditionally discharges the precharge node via the logic circuit conduction path to a discharged node voltage. The value of the discharged node voltage is intermediate to the precharged node voltage and the circuit reference node voltage (e.g. VSS=0). The inverter circuit inverts and buffers the precharged and discharged node voltages. In one embodiment, a bias voltage source, connected between the N-type discharge MOSFET and the reference node, provides a bias voltage which is intermediate to the precharged and reference node voltages, and the discharged node voltage is approximately equal to the bias voltage. In another embodiment, a pull-up MOSFET is connected to the discharge MOSFET for selectively providing a pull-up voltage which is intermediate to the precharged and reference node voltages, and the discharged node voltage is approximately equal to the pull-up voltage.

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