Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2007-04-10
2007-04-10
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S095000
Reexamination Certificate
active
10992488
ABSTRACT:
A dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control reduces power consumption of processors and other systems incorporating dynamic circuits. The power control signal may be a delayed version of the logic clock and turns on the output inverter foot device after the dynamic node has had sufficient time to evaluate, providing a fast evaluate time and reducing leakage through the inverter input when the foot device is off. Alternatively, a coarsely timed static power control signal may be used to control the inverter foot devices. The drains of the inverter foot devices can be commonly connected across multiple circuits, reducing the foot device total area.
REFERENCES:
patent: 5796282 (1998-08-01), Sprague et al.
patent: 5828234 (1998-10-01), Sprague
patent: 6069512 (2000-05-01), Rodriguez et al.
patent: 6288572 (2001-09-01), Nowka
patent: 6292027 (2001-09-01), Dhong et al.
patent: 6429689 (2002-08-01), Allen et al.
patent: 6459316 (2002-10-01), Vangal et al.
patent: 6570408 (2003-05-01), Nowka
patent: 6646487 (2003-11-01), Nedovic et al.
patent: 6690204 (2004-02-01), Belluomini et al.
patent: 6888377 (2005-05-01), Ngo et al.
patent: 6900666 (2005-05-01), Kursun et al.
patent: 2003/0189445 (2003-10-01), Ngo et al.
U.S. Appl. No. 10/965,106, filed Oct. 14, 2004, Deogun, et al.
Mutoh, et al., 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS, IEEE JSSC Issue V 30, # 8, 1995, USA, no date, no month.
Deogun Harmander Singh
Kleinosowski AJ
Kuang Jente Benedict
Ngo Hung Cai
Harris Andrew M.
Mitch Harris Atty at Law, LLC
Salys Casimer K.
Tan Vibol
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