Dynamic logic circuit and integrated circuit device using...

Details Dynamic logic circuit and integrated circuit device using... Dynamic logic circuit and integrated circuit device using...

1999-08-06

2001-08-21

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C326S112000, C326S119000

Reexamination Certificate

active

06278296

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dynamic logic circuit mounted on a CMOS semiconductor integrated circuit chip and a circuit included the dynamic logic circuit. In particular, the invention relates to a dynamic logic circuit operating at a high speed and a circuit including the dynamic logic circuit.
2. Description of the Related Art
FIG. 3
shows a prior art circuit disclosed in FIG. 4 of Japanese Patent Application No. 61-224623.
FIG. 4
shows another prior art circuit disclosed in FIG. 7 of Japanese Patent Application No. 61-224623. Although in Japanese Patent Application No. 61-224623, both of FIGS. 4 or 7 show an example circuit having five input signal lines, to simplify them, FIGS. 3 and 4 show prior art circuits each having three input signal lines.
In the prior art circuit of
FIG. 4
, when a clock signal
160
is at a low level, because a P-channel type MOS transistor
100
is conducted and a N-channel type MOS transistor
400
is cut off, an internal signal
171
becomes a high level and an output signal
170
becomes a low level despite the status of input signals
151
and
153
. This status is called a precharged status. Thereafter, when the clock signal
160
becomes a high level, the P-channel type MOS transistor
100
is cut off and the N-channel type MOS transistor
400
conducts. At this moment, when at least one of the input signals
151
through
153
is at a low level, the internal signal
171
becomes a floating status and is held at a high level and the output signal
170
is held at a low level. Further, when all of input signals
151
through
153
become a high level, the internal signal
171
becomes a low level and the output signal
170
becomes a high level because N-channel type MOS transistors
101
and
103
conduct. Accordingly, when at least one of input signals
151
through
153
is at a low level, an output signal becomes a low level and when all of the input signals
151
through
153
become a high level, then the output signal becomes a high level. In other words, the circuit in
FIG. 4
is operated as a AND circuit.
However, in
FIG. 4
, when the input signals
151
through
153
becomes a high level and the internal signal
171
is in a high-to-low transition, a current flows through a series of four MOS transistor
103
,
102
,
101
and
400
despite only three input signals. Accordingly, there is a problem when a time taken from all of input signals being a high level to the internal signal
171
being in a low-to-high transition (and the output signal
170
being in a low-to-high transition) is longer than a time from when three MOS transistors are used.
FIG. 3
is a prior example circuit that improves the prior art circuit of FIG.
4
. Although the circuit in
FIG. 3
operates as an AND circuit just as the circuit in
FIG. 4
, when the input signals
151
through
153
become a high level and the internal signal
171
is in a high-to-low transition, a short period of time is allowed as compared with the circuit of
FIG. 4
because a current flows through the three MOS transistors
103
,
102
and
101
.
SUMMARY OF THE INVENTION
In the circuit of
FIG. 3
, when a clock signal
160
becomes a low level at the time when all of the input signals
151
through
153
are a high level, a wasteful current flows from a power supply Vdd to a power supply Vss, via a P-channel type MOS transistor
100
and N-channel type MOS transistors
103
through
101
. This current is called a through current.
In the aforementioned Japanese Patent Application No. 61-224623, it is described that when conductance of P-channel type MOS transistors
100
or
300
are made small, a through current becomes small. However, when a conductance of a P-channel type MOS transistor
100
is made small, a time required for the precharge becomes long because a current for charging a stray capacity floating at a node of the internal signal
171
at the time of the precharge is decreased.
An object of the present invention is therefore, to decrease a through current and to reduce a time required for the precharge while a signal propagation delay time from all of input signals being a high level to an output signal
170
being in a low-to-high transition is regulated not to be long.
An object of the present invention is to provide a circuit in which:
a clock signal is input, a plurality of input signals are input, an output signal is output, the output signal is set to a second level at the time the clock signal is a first level and the output signal is set to a level determined by the plurality of input signals at the time the clock signal is a reverse level of the first level,
and to provide a circuit for controlling a level of the plurality of input signal in response to the clock signal.
Another object of the present invention is to provide in a dynamic logic circuit configured in which:
at the time a clock signal is a first level, an output signal becomes a second level, at the time the clock signal is a reverse level of the first level, the output signal becomes a desired level determined by a plurality of input signals,
and to provide means for regulating at least one of the plurality of input signals forcibly to be the second level.
Another object of the present invention is to provide in a dynamic logic circuit configured in which:
there is provided a first MOS transistor of a first conductive type whose source electrode is connected with a first power supply and whose gate electrode is connected with a clock signal and also provided a second MOS transistor of a second conductive type, different from the first conductive type whose source electrode is connected with a second power supply, whose gate electrode is connected with a first input signal and whose drain electrode is connected with a drain electrode of the first MOS transistor directly or via other MOS transistors, and an output signal is taken and from a drain electrode of the first MOS transistor,
a third MOS transistor connected between a gate electrode of the second MOS transistor and the second power supply.


REFERENCES:
patent: 5852373 (1998-12-01), Chu et al.
patent: 5926038 (1999-07-01), Fouts et al.
patent: 5936449 (1999-08-01), Huang
patent: 5999019 (1999-12-01), Zheng et al.
patent: 6075386 (2000-06-01), Naffziger
patent: 58-79338 (1983-05-01), None
patent: 61-224623 (1986-10-01), None
patent: 63-93223 (1988-04-01), None
Fundamentals of Digital Systems Design ( Rhyne, NJ, 1973, pp. 70-71).

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