Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2000-04-28
2002-04-23
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S093000, C326S095000, C326S097000, C326S121000
Reexamination Certificate
active
06377080
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to logic circuits and more particularly to a logic circuit including a dynamic logic stage driving a dynamic evaluation stage, wherein the dynamic evaluation stage responds to an output signal of the dynamic logic stage for only an initial segment of a first portion of each cycle of a clock wave.
BACKGROUND ART
FIG. 1
is a circuit diagram of a dynamic logic circuit previously developed by an employee of the assignee of the present application. The circuit illustrated in the diagram of
FIG. 1
has not, to my knowledge, been offered for sale or disclosed on a non-confidential basis to third parties.
The circuit of
FIG. 1
includes dynamic logic stage
10
, dynamic evaluation stage
12
, and inverter, driver stage
14
. The circuitry of
FIG. 1
is complementary metal oxide semiconductor (CMOS) circuitry on an integrated circuit chip (not shown).
The circuit of
FIG. 1
is responsive to binary data input signals IN
0
, IN
1
. . . IN
n
and a clock pulse train (CK) preferably having a high frequency, such as 1 gigahertz (GHz). The clock pulse train has approximately a 50 percent duty cycle so each half cycle of the 1 GHz clock pulse train has a period of approximately 500 picoseconds. First and second opposite DC power supply terminals or rails
18
and
20
are, in a preferred arrangement, respectively at +V
DD
(+1.3) volts and ground. CMOS dynamic logic stage
10
, in the illustrated configuration, includes n N-channel field effect transistors (FETs)
22
0
,
22
1
. . .
22
n
, having gate electrodes respectively responsive to binary input signals IN
0
, IN
1
. . . IN
n
and parallel source drain paths connected in shunt between leads
24
and
26
. Dynamic logic stage
10
also includes P-channel field effect transistor
28
and N-channel field effect transistor
30
, each having a gate electrode responsive to the clock pulse wave train CK. Field effect transistor
28
has its source drain path connected between lead
24
and positive power supply terminal rail
18
, while the source drain path of transistor
30
is connected between ground rail
20
and lead
26
.
During alternate half cycles of the CK clock pulse wave train, when the clock pulse wave train has a low voltage (CK=0, approximately equal to the. ground potential at rail
20
), the clock pulses cause the source drain paths of field effect transistors
28
and
30
to respectively have low and high impedances. The low impedance of field effect transistor
28
connects lead
24
to the positive power supply voltage on terminal or rail
18
and the relatively high source drain impedance of transistor
30
decouples lead
26
from ground rail
20
to enable parasitic capacitance
29
between lead
24
and ground to be precharged. Hence, during the alternate half clock cycles while CK has a low value, capacitance
29
is precharged to a high voltage (i.e., true or binary 1 level).
During the remaining alternate half cycles of the CK clock pulse wave train, while the clock pulse wave train has a high value (approximately equal to the voltage at rail
18
), the clock causes the source drain path of field effect transistor
30
to be switched on to provide a low impedance that connects lead
26
to ground simultaneously with the source drain path of field effect transistor
28
being off to provide a high impedance that establishes a load impedance for the voltage developed at lead
24
. Evaluation stage
12
detects whether the voltage on parasitic capacitance
29
is high or low while CK=1. Capacitance
29
remains charged to the high voltage while CK=1 only if all of IN
0
, IN
1
. . . IN
n
have low voltages associated with binary 0 values. If any of IN
0
, IN
1
. . . IN
n
has a high voltage, associated with a binary 1 value while CK=1, the source drain paths of transistor
30
and the transistor(s)
22
0
,
22
1
. . .
22
n
having gate(s) responsive to a binary 1 signal provide a low impedance path from lead
24
through transistor
30
to discharge capacitance
29
essentially to ground. Based on the foregoing, field effect transistors
22
0
,
22
1
. . .
22
n
are connected and function as a NOR logic gate during the clock pulse half cycle while CK=1.
Dynamic evaluation stage
12
responds to the bi-level binary logic signal on capacitance
29
to produce a bi-level output signal designed to have a value complementary to the signal on lead
24
during the clock pulse half cycles while CK=1. CMOS dynamic evaluation stage
12
includes complementary P-channel field effect transistor
36
and N-channel field effect transistor
34
having series connected source drain paths and gate electrodes driven in parallel by the bi-level binary logic signal on capacitance
29
. The source drain paths of transistors
34
and
36
are also series connected with the source drain path of N-channel field effect transistor
38
, having a gate electrode driven by the CK clock pulse wave train. The source drain paths of field effect transistors
34
,
36
and
38
are series connected between power supply rails
18
and
20
so that the sources of field effect transistors
36
and
38
are respectively tied to +V
DD
rail
18
and ground rail
20
.
The drains of transistors
34
and
36
have a common terminal
40
, where the bi-level output signal of dynamic evaluation stage
12
is derived. Terminal
40
is tied to the gate of P-channel field effect transistor
42
, having a source drain path connected between lead
24
and positive DC power supply rail
18
, so that the source drain path of field effect transistor
42
shunts the source drain path of field effect transistor
28
.
Field effect transistors
34
and
36
function as an inverter for the bi-level logic signal precharged on parasitic capacitance
29
while CK=1 turns on the source drain path of field effect transistor
38
. Consequently, if the voltage on capacitance
29
is high while CK=1, the voltage at terminal
40
is low. The low voltage at terminal
40
forward biases the gate of transistor
42
to turn on the source drain path of transistor
42
which thereby supplies +V
DD
to capacitance
29
to maintain the voltage on capacitance
29
at the high value. If the voltage on capacitance
29
is precharged low while CK=1, the inverter comprising transistors
34
and
36
supplies a high voltage to terminal
40
. The high voltage at terminal
40
back biases the source drain path of transistor
42
so the source drain path of transistor
42
does not couple +V
DD
at rail
18
to capacitance
29
while CK=1 and the voltage across capacitance
29
remains low.
To assure that the voltage at terminal
40
is high, at +V
DD
, during the half cycles of the clock pulse wave train while CK=0, the source drain path of P-channel field effect transistor
44
is connected between terminal
40
and the positive power supply voltage +V
DD
at rail
18
and the gate of field effect transistor
44
is connected to be responsive to the clock pulse wave train. Thereby, during the half cycles of the clock pulse wave train while CK=0, the source drain path of field effect transistor
44
has a low impedance, to tie the voltage at terminal
40
substantially to the +V
DD
voltage on rail
18
.
Inverter
14
, which also functions as a driver, responds to the bi-level signal on terminal
40
. Inverter
14
has the usual construction, including complementary P-channel field effect transistor
46
and N-channel field effect transistor
48
, having series connected source drain paths connected between +V
DD
power supply rail
18
and ground rail
20
. Field effect transistors
46
and
48
have gate electrodes driven in parallel by the bi-level signal at terminal
40
and common drain electrodes at output terminal
50
of the circuit of FIG.
1
. During the half cycles of the clock pulse wave train while CK=1, the binary level at terminal
50
is supposed to be the same as the prech
Hewlett--Packard Company
Paik Steven S.
Tokar Michael
LandOfFree
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