Dynamic logic circuit

Details Dynamic logic circuit Dynamic logic circuit

1996-12-20

1999-01-12

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326121, 326 95, H03K 19003

Patent

active

058595473

ABSTRACT:
A dynamic logic circuit that uses substantially constant power and that has substantially constant propagation delay, independent of the number of inputs the dynamic logic circuit contains. In one embodiment of the circuit, an evaluation transistor is positioned between a precharge transistor and a dynamic logic block. The evaluation transistor separates a precharge node from the logic block during a precharge clock phase so that the logic block is not charged. A delay coupled to the precharge transistor allows the precharge transistor to remain activated during a portion of an evaluation clock phase to overcome any effects of charge-sharing between the precharge node and the dynamic logic block. Because the evaluation transistor separates the logic block from the precharge node, the precharge node can be charged independently of the number of inputs present in the dynamic logic block.

REFERENCES:
patent: 4569032 (1986-02-01), Lee
patent: 4692637 (1987-09-01), Shoji
patent: 4700086 (1987-10-01), Ling et al.
patent: 4849658 (1989-07-01), Iwamura et al.
patent: 4899066 (1990-02-01), Aikawa et al.
patent: 5008569 (1991-04-01), Roy
patent: 5023486 (1991-06-01), Gongwer
patent: 5070262 (1991-12-01), Hashimoto
patent: 5208489 (1993-05-01), Houston
patent: 5402012 (1995-03-01), Thomas
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5530380 (1996-06-01), Kondoh
Goncalves et al., "NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures," IEEE Jour. Sol-Sta Cir, vol. Sc-18, No. 3, pp. 261-266 (Jun. 1983).
Krambeck et al., "High-Speed Compact Circuits with CMOS," IEEE Jour. Sol-Sta Cir, vol. SC-17, No. 3, pp. 614-619 (Jun. 1982).
Lee et al., "Zipper CMOS," IEEE Circuits and Devices Magazine, vol. 2, pp. 10-16 (May 1986).
Weste et al., "5.4.7 CMOS Domino Logic," Chap. 5, Principles of CMOS VLSI design: a systems perspective, Library of Congress, 2nd ed., pp. 308-344 (1993).

Affiliated with

Also associated with

Rating

Dynamic logic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic logic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic logic circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1519963