Dynamic latching logic structure with static interfaces for...

Details Dynamic latching logic structure with static interfaces for... Dynamic latching logic structure with static interfaces for...

2007-01-09

2007-01-09

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S093000, C326S098000

Reexamination Certificate

active

10926897

ABSTRACT:
A latching dynamic logic includes a dynamic logic gate, a static logic input interface, and a set-reset output latch. The dynamic logic gate receives a clock signal, a data signal, and a select signal output of the static logic input interface. The dynamic logic gate includes a dynamic node and a pulldown network coupled to the dynamic node. The pulldown network selectively discharges the dynamic node following a clock signal transition dependent on the data signal and the select signal output of the static logic input interface being active. The set-reset output latch is coupled to the dynamic node of the dynamic logic gate for providing an output signal.

REFERENCES:
patent: 6744282 (2004-06-01), Dhong et al.

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