Dynamic latch having integral logic function and method...

Details Dynamic latch having integral logic function and method... Dynamic latch having integral logic function and method...

2007-01-16

2007-01-16

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C327S200000

Reexamination Certificate

active

10902204

ABSTRACT:
A circuit (50) that receives dynamic signals performs both logic and latching to achieve high speed operation. The circuit has a clock that defines both an evaluation phase and a precharge phase in which the dynamic signals are evaluated during the evaluation phase. The circuit (50) functions by precharging a latch node (INT) during the evaluation phase then performing evaluation as well during the evaluation phase. The evaluation results in providing a valid logic state to the latch node. A latch circuit (54) latches this valid state during the precharge phase and holds it in this valid state during the precharge phase. This can be adapted to select which one of the dynamic signals is to be coupled and latched on the latch node (INT).

REFERENCES:
patent: 5852373 (1998-12-01), Chu et al.
patent: 6052008 (2000-04-01), Chu et al.
patent: 6087872 (2000-07-01), Partovi et al.
patent: 6239622 (2001-05-01), Harris
patent: 6337584 (2002-01-01), Davies et al.
patent: 6570407 (2003-05-01), Sugisawa et al.

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