Dynamic instruction and data updating architecture

Details Dynamic instruction and data updating architecture Dynamic instruction and data updating architecture

2006-11-15

2011-12-06

Li, Aimee (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Data driven or demand driven processor

C712S225000

Reexamination Certificate

active

08074053

ABSTRACT:
A memory update engine provides flexible modification of data in memory. A processor may employ the update engine to update filter coefficients, special effects parameters, signal sample processing instructions, or any other instruction or data during processing. The update engine supports dynamic updating without requiring processor shutdown, thereby allowing the processor to seamlessly continue operation during a live performance.

REFERENCES:
patent: 4903259 (1990-02-01), Hayano
patent: 5226131 (1993-07-01), Grafe et al.
patent: 5519449 (1996-05-01), Yanai et al.
patent: 5542059 (1996-07-01), Blombren
patent: 5680175 (1997-10-01), Yanai et al.
patent: 5927218 (1999-07-01), Tretter
patent: 5977881 (1999-11-01), Kido
patent: 6052792 (2000-04-01), Mensch, Jr.
patent: 6195665 (2001-02-01), Jarett
patent: 6278718 (2001-08-01), Eschholz
patent: 6421274 (2002-07-01), Yoshimura
patent: 6462743 (2002-10-01), Battle
patent: 2002/0056034 (2002-05-01), Gearty et al.
patent: 2005/0206660 (2005-09-01), Kanai
patent: 2006/0262965 (2006-11-01), Sugita et al.
patent: 2007/0073798 (2007-03-01), Donofrio et al.
patent: 2007/0074008 (2007-03-01), Donofrio et al.
patent: 195 29 718 (1997-02-01), None
patent: 1 517 331 (2005-03-01), None
patent: 63107399 (1988-05-01), None
patent: WO 03/003237 (2003-01-01), None
patent: WO 2005/069121 (2005-07-01), None
John L. Hennessy and David A. Patterson, “Pipelining: Basic and Intermediate Concepts” Appendix A, pp. A2-A81, Computer Architecture A Quantitative Approach, Third Edition, 2003.
John L. Hennessy and David A. Patterson, “Enhancing Performance with Pipelining” Chapter 6, pp. 436-536, Computer Organization & Design, Second Edition, 1997.

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