Dynamic impedance controlled driver for improved slew rate...

Details Dynamic impedance controlled driver for improved slew rate... Dynamic impedance controlled driver for improved slew rate...

2001-03-29

2002-09-10

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S026000, C326S027000

Reexamination Certificate

active

06448807

ABSTRACT:

FIELD OF THE INVENTION
Embodiments of the present invention relate to a dynamic impedance controlled driver which gives improved slew rate and glitch termination when driving a signal having edge transmissions over a transmission line.
BACKGROUND OF THE INVENTION
As system performance has increased, associated input and output delays have decreased. Recent high-speed requirements have forced output buffer designers to push buffer driver impedance much lower than the transmission line impedance they are driving in order to meet timings. This is due to the far end receiver requiring the received signal to be driven to required specifications with multiple loads within a single time of flight. Multiple loads often result in parallel transmission lines and reduced transmission line impedance where the transmitted signal energy is shared among each path.
Simultaneous switching noise can propagate from the power supply rails of an aggressor buffer's (the one switching), through a victim buffer (one not switching), and onto its transmission line. As the driver impedance becomes less than the line impedance, the energy transferred onto the transmission line increases.
A need, therefore, exists for an improved termination arrangement reduces or addresses these problems.


REFERENCES:
patent: 5528166 (1996-06-01), Iikbahar
patent: 5898321 (1999-04-01), Likbahar et al.
patent: 5963047 (1999-10-01), Kwong et al.
patent: 6242942 (2001-06-01), Shamarao
patent: WO 99/06845 (1999-11-01), None

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