Patent
1997-01-10
1997-11-18
Harvey, Jack B.
395292, 395729, 395732, G06F 1300
Patent
active
056896565
ABSTRACT:
A method of prioritizing computer resource access requests to a shared computer resource, such as a video frame buffer, includes the steps of providing a number, n, of priority schemes in correspondence with a like number of potentially requesting entities, where n is an integer greater than one, and where each priority scheme designates relative priority of the potentially requesting entities with respect to one another. Thus, for each priority scheme there exists one corresponding potentially requesting entity, and a number, n-1, of noncorresponding potentially requesting entities. Next, one of the priority schemes is selected for use as a current priority scheme. A set of currently requesting entities is then determined from the number of potentially requesting entities, and the current priority scheme is used to select a highest priority requesting entity from the set of currently requesting entities. Finally, one of the priority schemes is newly selected as the current priority scheme, wherein the newly selected priority scheme corresponds to the highest priority requesting entity. In one embodiment, at least one of the priority schemes designates a first priority for the corresponding potentially requesting entity, and a second priority for one of the noncorresponding potentially requesting entities, where the first priority is higher than the second priority. In another aspect of the invention, at least one of the potentially requesting entities has a same relative priority designation in at least two of the n priority schemes.
REFERENCES:
patent: 5257348 (1993-10-01), Roskowski et al.
patent: 5263138 (1993-11-01), Wasserman et al.
patent: 5274753 (1993-12-01), Roskowski et al.
patent: 5301272 (1994-04-01), Atkins
patent: 5388228 (1995-02-01), Heath et al.
PowerPC 601 RISC Microprocessor User's Manual, pp. 2-42 through 2-70; 8-1 through 8-36; and 9-1 through 9-52, published by Motorola in 1993.
PCI Local Bus Specification, Review Draft Revision 2.1, published Oct. 21, 1994 by the PCI Special Interest Group, P.O. Box 14070, Portland, OR 97214.
PCI Multimedia Design Guide, Revision 1.0 (Mar. 29, 1994), which is distributed by the PCI Multimedia Working Group (part of the PCI Special Interest Group, P.O. Box 14070, Portland, OR 97214).
Baden Eric A.
Childers Brian A.
Apple Computer Inc.
Harvey Jack B.
Pancholi Jigar
LandOfFree
Dynamic hierarchical arbitration of computer resource access req does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic hierarchical arbitration of computer resource access req, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic hierarchical arbitration of computer resource access req will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1572967