Electrical computers and digital processing systems: support – Computer power control
Reexamination Certificate
2005-05-03
2005-05-03
Fleming, Fritz M. (Department: 2182)
Electrical computers and digital processing systems: support
Computer power control
C713S320000, C713S323000, C307S038000
Reexamination Certificate
active
06889330
ABSTRACT:
A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list. As each task in a scenario is executed, a control word associated with the task can be used to enable/disable circuitry, or to set circuits to an optimum configuration.
REFERENCES:
patent: 5339445 (1994-08-01), Gasztonyi
patent: 5452277 (1995-09-01), Bajorek et al.
patent: 5557557 (1996-09-01), Frantz et al.
patent: 5623647 (1997-04-01), Maitra
patent: 5692204 (1997-11-01), Rawson et al.
patent: 5719800 (1998-02-01), Mittal et al.
patent: 5781783 (1998-07-01), Gunther et al.
patent: 5860106 (1999-01-01), Domen et al.
patent: 5944829 (1999-08-01), Shimoda
patent: 5977964 (1999-11-01), Williams et al.
patent: 5996083 (1999-11-01), Gupta et al.
patent: 6076140 (2000-06-01), Dhong et al.
patent: 6298448 (2001-10-01), Shaffer et al.
patent: 6430693 (2002-08-01), Lin
patent: 6519706 (2003-02-01), Ogoro
patent: 6523123 (2003-02-01), Barbee
patent: 6530027 (2003-03-01), Morita
patent: 6609208 (2003-08-01), Farkas et al.
patent: 6625737 (2003-09-01), Kissell
patent: 6625740 (2003-09-01), Datar et al.
patent: 20020042887 (2002-04-01), Chauvel et al.
patent: 20020055961 (2002-05-01), Chauvel et al.
patent: 0 683 451 (1995-11-01), None
patent: 0 794 481 (1997-09-01), None
Texas Instruments Incorporated, U.S. Appl. No. 09/696,052, filed Oct. 25, 2000,Intelligent Power Management for Distributed Processing Systems.
R. Young, et al.;Adaptive Clock Speed Control for Variable Processor Loading, Motorola Technical Developments, Motorola, Inc., Schaumburg, IL, US, vol. 15, May 1, 1992, pp. 43-44.
I.A. Manzak, et al.;Variable Voltage Task Scheduling for Minimizing Energy or Minimizing Power, 2000 IEEE Int'l Conf. on Acoustics, Speech & Signal, vol. 6, Jun. 5, 2000, pp. 3239-3242.
Chauvel Gerard
D'Inverno Dominique
Brady III W. James
Fleming Fritz M.
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Dynamic hardware configuration for energy management systems... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic hardware configuration for energy management systems..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic hardware configuration for energy management systems... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3381847