Dynamic gate with conditional keeper for soft error rate...

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C326S093000, C326S119000

Reexamination Certificate

active

07053663

ABSTRACT:
A dynamic logic gate with a conditional keeper, the conditional keeper comprising a pMOSFET pull-up that switches ON only after the dynamic logic gate completes an evaluation so as to avoid contention with the pull-down network. By sizing the conditional keeper to be stronger than the half-keeper, embodiments may realize a significant reduction in soft error rates that are latched.

REFERENCES:
patent: 5896046 (1999-04-01), Bjorksten et al.
patent: 6172531 (2001-01-01), Aipperspach et al.
patent: 6184718 (2001-02-01), Tran et al.
patent: 6529045 (2003-03-01), Ye et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Dynamic gate with conditional keeper for soft error rate... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic gate with conditional keeper for soft error rate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic gate with conditional keeper for soft error rate... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3544937

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.