Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1997-09-23
2000-06-20
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711118, 711141, G06F 1200
Patent
active
060790024
ABSTRACT:
A method and system in a data processing system for accessing information using an instruction specifying a memory address is disclosed. The method and system comprises issuing the instruction to an execution unit and storing an address derived from the specified address. The method and system also includes accessing a cache to obtain the information, using the derived address and determining, in response to a signal indicating that there has been a cache miss, if there is a location available to store the specified address in a queue. According to the system and method disclosed herein, the present invention allows for dynamic pipeline expansion of a processor without splitting this function between components depending upon the reason expansion was required, thereby increasing overall system performance.
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Hicks Troy Neal
Muhich John Stephen
Thatcher Larry Edward
White Steven Wayne
Bataille Pierre-Michel
Cabeca John W.
England Anthony V.S.
International Business Machines - Corporation
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