Dynamic event recognition

Details Dynamic event recognition Dynamic event recognition

2000-08-03

2003-07-29

Baderman, Scott (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C709S241000

Reexamination Certificate

active

06601193

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to an event recognition unit for recognizing and/or monitoring events on an information bus.
There are several possibilities known in the art to recognize events in a data processing unit such as a personal computer (PC), a workstation, or the like. The term ‘event’, as used herein, shall refer to any kind of occurrence of significance, e.g. a dead lock situation (‘transfer does never complete’), a dead system (‘no bus traffic after x clocks’), an access to an address A by an agent B, or the like.
Events occurring in the data processing unit are normally recognized (and might further be captured) by monitoring data communication facilities such as data busses, whereby the term ‘data bus’ shall refer to any kind of data connection as known in the art.
FIG. 1
depicts an event counter
5
for real-time counting as a device for event recognition as known in the art. A comparator
10
receives at least one input signal to be observed on an input bus
20
. The comparator
10
monitors the input bus
20
for a predefined-pattern (also referred to as pattern terms) and provides a count signal on a line
30
to a counter
40
, e.g. a logical ‘1’ in case of an observed event (i.e. the predefined pattern has been detected). Generally speaking, a pattern (term) is a logical term which can result in either a logical ‘0’ or a logical ‘1’. It can comprise any logical relationship between bus patterns and pre-programmed terms. These relationships can be mask/value combinations (like “AD
32
==000b8xxx\h”), ranges (like “signal <=7 && signal >1”), lists (like “cmd==7|cmd==3|cmd==9”), or the like. It can be generally stated that a pattern term's value consists of a variable part and of a fixed part.
A pattern on input bus
20
is detected when for each of the signals, that input bus
20
consists of, one of the following conditions is met: the input signal is in the logical ‘0’ state or in the logical ‘1’ state or is in any logical state (don't care), dependent on its specification. The number of events in the input signal on the input bus
20
is thus counted by the counter
40
.
The term ‘counters’ as used herein shall apply to devices, such as registers or storage locations, which are used to represent a number of occurrences of an event. Counters are normally used in conjunction with a filter or trigger module for real time counting of a specific event.
The comparator
10
, or another filter or trigger module, ergo selects, according to the predefined pattern, whether or not the occurred event will be counted by the counter
40
. A more illustrative example to understand the function of the conventional event counter
5
could be a task to measure all red cars traveling from a point A to a point B. The comparator
10
(as filter or trigger task) would select the red cars on the input bus
20
only and send this information via line
30
to the counter
40
which counts the number of red cars as the filtered or triggered events.
Event counters
5
are often applied for performance measurement purposes. The performance represents the degree to which a system or component accomplishes its designated function within given constraints, such as speed accuracy or memory usage. The performance can be defined e.g. by the ratio of the number of specific events to all events, or by the number of events per time unit.
For performance measurements (e.g. ‘the percentage of red cars’), the input bus
20
might further be coupled to an input information counter
50
counting all events in the input signal on the input bus
20
, whereas the event counter
5
will only count specific events defined by the specific pattern. The counter
40
of the event counter
5
and the input information counter
50
are coupled to a processing unit
60
which determines the performance on the input bus
20
, e.g., by dividing the content of counter
40
by the content of the input information counter
50
. The input information counter
50
can basically be built up in accordance with the event counter
5
.
The information as received from the performance measurement according to
FIG. 1
provides only a limited information about the actual performance on input bus
20
which might not be sufficient for certain applications.
Another known device for event evaluation is a so-called trace memory
70
. The trace memory
70
comprises an event recognizer
80
which is coupled via a line
85
to a memory
90
for controlling a read/write access of the memory
90
on the input bus
20
. The memory
90
stores events recognized by the event recognizer
80
. The trace memory
70
thus allows to reproducible ‘trace’ events e.g. for logic analyzing. The event recognizer
80
normally allows—dependent on a recognized event—to either move to a successive state, to jump to a predefined state, or to stay in the current state. This, however, might not be sufficient for applications that are more complex.
For the purpose of initiating bus transactions (i.e. a write access to a system memory via a PCI bus), a system Hewlett-Packard HP E2910A, introduced by the applicant, uses a plurality of comparators in combination with a sequencer state machine as an event recognition unit
100
, as depicted in FIG.
2
. The event recognition unit
100
comprises one or more comparators
110
a
. . .
110
z
coupled to an information bus
120
. An output of each one of the comparators
110
a
. . .
110
z
is coupled via a line
130
a
. . .
130
z
to a sequencer state machine
140
. The sequencer state machine
140
comprises a memory
142
and a register
144
, whereby one or more outputs of the register
144
are coupled back to one or more inputs of the memory
142
as indicated by line
146
. The coupling back allows the sequencer state machine
140
to move between different states, whereby the specific state of the sequencer state machine
140
is not constant but depends on the history of information as provided thereto. The sequencer state machine
140
further receives a clock signal CLOCK on a line
150
, and eventually provides an output bus
160
for initiating the bus transactions.
In the HP E2910A, the comparators
110
a
. . .
110
z
monitor the information bus
120
for predefined event-patterns (in accordance with comparator
10
in
FIG. 1
) and thus signal occurring events to the sequencer state machine
140
. The sequencer state machine
140
moves from one state to a next state according to the information as provided on its inputs
130
a
. . .
130
z
,
146
, and
150
. When the sequencer state machine
140
reaches a certain predefined state, it will initiate a corresponding bus transaction by means of respective output signals applied to the output bus
160
.
A system Hewlett-Packard HP E2925A, again introduced by the applicant, uses the concept of the event recognition unit
100
for analyzing data streams on the information busses
120
a
. . .
120
z
e.g. for applied protocols or information data, thus allowing monitoring and analyzing time information and correlations between events.
FIG. 3
shows a data-analyzing unit
200
of the Hewlett-Packard HP E2925A. The data-analyzing unit
200
comprises an event recognition unit
205
as an enhancement of the event recognition unit
100
. The one or more comparators
110
a
. . .
110
z
are coupled to one or more information busses
120
a
. . .
120
z
, respectively. The information busses
120
a
. . .
120
z
can represent one single information line, a plurality of individual information busses, or combinations thereof, and may also be coupled to one information bus
120
. A sequencer state machine
140
A according to the invention, which basically corresponds to the sequencer state machine
140
, may further receive a clock signal CLOCK on a line
150
, and provides one or more output busses
160
a
. . .
160
z
. The sequencer state machine
140
A will move from one state to a next state according to the

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