Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
1999-11-15
2003-10-07
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S266000
Reexamination Certificate
active
06631434
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for providing dynamic early indications for a computer subsystem function that informs a processor to perform associated processing.
DESCRIPTION OF THE RELATED ART
Computers typically include several subsystems that perform one or more predetermined or desired functions, such as functions associated with data transfer, communications, data processing, etc. It is often desired to inform a processor or central processing unit (CPU) of the computer to perform processing associated with one or more of the subsystem functions. In this manner, the subsystem cooperates with the CPU by completing a task or operation and informing the CPU of the completed task so that the CPU may perform further processing. For example, an expansion or adapter card may be plugged into a peripheral bus of a computer that transfers data to the main memory of the computer. The expansion card sends an interrupt to the CPU after the data is transferred, so that the CPU may execute an interrupt handling routine to process the data.
Significant delay may occur between the time the interrupt is asserted until the CPU begins the associated processing in response to the interrupt. Such delays may arise from several sources, such as from bus and logic latency while transferring the interrupt to interrupt handling logic, and/or from the CPU completing a current task and executing an interrupt service routine (ISR) or driver associated with the particular type of interrupt. Such delays cause inefficiency of the subsystem, which may affect the overall performance of the computer system.
One exemplary subsystem is network communications such as performed by a network adapter card or network interface controller (NIC). Computers and other devices may be networked together using any one of several available architectures and any one of several corresponding and compatible network protocols. A common network architecture is Ethernet™, such as the 10Base-T Standard operating at 10 Megabits per second (Mbps) and 100Base-TX Ethernet™ Standard operating at 100 Mbps according to the IEEE Standard 802.3. A newer Ethernet™ architecture operating at 1 Gigabit per second (Gbps) is available and becoming more prominent for server systems. The present invention is illustrated using the Ethernet™ architecture and TCP/IP (Transmission Control Protocol/Internet Protocol), which is a common network protocol particularly for the Internet. The present invention, however, is not limited to any particular network protocol or architecture. In fact, although the present invention is illustrated using network type communication systems, it is not limited to network communications and may be applied to any type of subsystem of a computer.
A computer typically includes a bus system with corresponding slots for receiving compatible network adapter expansion cards, such as NICs, for interfacing the computer to a network. Each NIC includes an appropriate connector for interfacing a compatible network cable, such as a coaxial cable, a twisted-wire cable, a fiber optic cable, etc. For example, in an Ethernet™ star configuration, each NIC includes an RJ-45 connector for receiving a compatible RJ-45 plug of a twisted-wire cable, where each network cable is coupled to a central device such as a repeater, hub, switch, etc. The bus system may include one or more of several standard or proprietary buses, such as the Peripheral Component Interconnect (PCI), the Industry Standard Architecture (ISA) bus, the Extended ISA (EISA) bus, the MicroChannel Architecture (MCA) bus, etc., as well as a host bus and an input/output (I/O) extension bus, sometimes called the “X-bus”. The NIC also includes a compatible connector to plug into a corresponding bus of the host computer system. For example, A PCI compatible NIC including a PCI connector is common for servers.
The primary function of the NIC is to transfer data to and from system memory of the computer system, although the NIC may perform many other network functions. A NIC may have its own processor or processing logic, but many network functions may still require processing by the main processor or central processing unit (CPU) of the host computer system. For example, a NIC often includes Direct Memory Access (DMA) circuitry or the like for transferring data between the NIC and the system memory. After transferring data from the network to the computer system memory, however, the computer CPU may be needed to process the transferred data in the system memory. In a similar manner, when data is transferred from the system memory to the NIC or asserted onto the network, the NIC may inform the CPU that the transfer has completed so that the CPU may perform associated functions or processing.
The NIC asserts an indication or interrupt to inform the host CPU that processing by the CPU associated with a network function is necessary. A certain amount of interrupt latency exists between when the interrupt is asserted and when the host CPU executes a driver associated with the NIC in response to the interrupt to handle network associated processing. The interrupt latency is caused by several factors, such as delay caused by the computer bus system when transferring the interrupt to the appropriate interrupt handling circuitry of the computer. The host CPU may cause further interrupt delays, since it typically must complete any current processing and usually must locate and execute the NIC driver to handle the interrupt.
One or more computers in a network configuration may operate as servers for other computers and devices in the network. Often, the other computers and devices rely on the server(s) for information, storage, access to databases, programs, other networks, etc., and various other services. It is desired to improve network processing between a network adapter or NIC and its host computer for any computer coupled to a network. This is particularly true when the computer operates as a server on the network. It is desired that each server operate as efficiently as possible and to provide as much data bandwidth as possible, especially during periods of heavy demand and increased network traffic. More generally, it is desired to improve the efficiency of processing associated with any type of subsystem of a computer.
SUMMARY OF THE INVENTION
A dynamic early indication system according to the present invention includes a processor, subsystem logic that performs a subsystem function to be reported to the processor, an early indicator, indication logic that provides an indication to inform the processor that processing associated with the subsystem function is needed at a completion time of the subsystem function, and a driver that is executed by the processor in the response to the indication to perform the subsystem processing. The indication logic provides the indication prior to the completion time of the subsystem function if the early indicator indicates early indication. Also, the driver, when executed by the processor, controls the early indicator in an attempt to improve efficiency of the subsystem processing.
In one embodiment, a memory is included and coupled to the processor, where the subsystem function is associated with transferring data between the network and the memory of the computer system. In this case, the completion time corresponds to when data has been completely stored in the memory. The indication logic calculates or otherwise estimates the completion time using a known or otherwise determined data transfer rate and the amount of data to be transferred and calculates an early time using the calculated completion time and a predetermined early time offset. In this manner, the indication logic provides the indication at the early time if so indicated by the early indicator, such as before the completion time by an amount of time corresponding to the predetermined early time offset.
The early indicator may be an early logic bit that determines whether early indication is to be used. For example, if the early bi
Canion Rodney S.
Johnson Scott C.
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