Dynamic disablement of a transaction ordering in response to an

Details Dynamic disablement of a transaction ordering in response to an Dynamic disablement of a transaction ordering in response to an

1998-05-27

2000-12-19

Follansbee, John A.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

710 28, 714 9, G06F 300

Patent

active

061638153

ABSTRACT:
An apparatus and method of transmitting data from a PCI 2.1 compliant device is provided. PCI devices (i.e., PCI bridges) designed in accordance with the 2.1 PCI specification have a load data ordering feature that prohibits load data to bypass DMA write data in the bridge. The present apparatus and method allow load data to bypass DMA write data in the PCI bridge if the bridge is in an error state.

REFERENCES:
patent: 5140679 (1992-08-01), Michael
patent: 5448704 (1995-09-01), Spaniol et al.
patent: 5455915 (1995-10-01), Coke
patent: 5535340 (1996-07-01), Bell et al.
patent: 5535341 (1996-07-01), Shah et al.
patent: 5546546 (1996-08-01), Bell et al.
patent: 5548730 (1996-08-01), Young et al.
patent: 5613075 (1997-03-01), Wade et al.
patent: 5613153 (1997-03-01), Arimilli et al.
patent: 5613162 (1997-03-01), Kabenjian
patent: 5621902 (1997-04-01), Cases et al.
patent: 5623697 (1997-04-01), Bland et al.

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