Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2005-04-05
2005-04-05
Rinehart, Mark H. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S105000, C710S056000
Reexamination Certificate
active
06877060
ABSTRACT:
An input circuit is coupled to a first bus to transfer a delayed transaction (DT) data having a transaction identifier to one of N buffers. The input circuit is dynamically configured according to a bus frequency. N is a positive integer. The one of the N buffers is associated with the transaction identifier. An output circuit is coupled to the buffers to transfer the DT data from the one of the N buffers to a second bus operating at the bus frequency. The output circuit is dynamically configured according to the bus frequency.
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Arthur J. Bernstein, David S. Gerst, Wai-Hong Leung, and Philip M. Lewis, “Design and Performance of an Assertional Concurrency Control System”, 1998, University of New York at Stony Brook, Data Engineering, 1998. Proceedings., 14th International Conf..
Intel Corporation
King Justin I.
Rinehart Mark H.
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