Dynamic decoder input for semiconductor memory

Details Dynamic decoder input for semiconductor memory Dynamic decoder input for semiconductor memory

1980-03-21

1982-05-18

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Complementing/balancing

365174, G11C 1140

Patent

active

043308511

ABSTRACT:
A decoder for address inputs to a semiconductor memory or the like comprises a NOR gate having a number of parallel input transistors corresponding to the number of address bits to be decoded. The address bits and their complements are selectively connected to the gates of the input transistors and the sources of these transistors, rather than only to the gates as in prior decoders. The layout of this decoder more nearly matches the pitch of rows in a high density dynamic RAM.

REFERENCES:
patent: 4042915 (1977-08-01), Reed
patent: 4061999 (1977-12-01), Proebsting et al.

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