Dynamic decoder circuit operative at low frequency clock signals

Details Dynamic decoder circuit operative at low frequency clock signals Dynamic decoder circuit operative at low frequency clock signals

1994-02-02

1995-08-15

Hudspeth, David R.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326 97, H03K 190948

Patent

active

054423082

ABSTRACT:
A dynamic decoder stores decoded signals in latch circuits for producing output signals, and the latch circuits are disabled after storing the decoded signals so that the output signals are free from undesirable level change of the decoded signals due to leakage between the dynamic decoding operations.

REFERENCES:
patent: 4620116 (1986-10-01), Ozawa
patent: 4668880 (1987-05-01), Shoji
patent: 4769562 (1988-09-01), Ghisio
patent: 4827160 (1989-05-01), Okano
patent: 5250857 (1993-10-01), Miyazaki

Affiliated with

Also associated with

Rating

Dynamic decoder circuit operative at low frequency clock signals does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic decoder circuit operative at low frequency clock signals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic decoder circuit operative at low frequency clock signals will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2185125