Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2007-09-12
2009-08-11
Shin, Christopher B (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S105000, C711S157000, C711S167000
Reexamination Certificate
active
07574548
ABSTRACT:
As a performance critical (high or full speed) request for a computer system data bus travels down a central pipeline, the system detects whether the interface data bus is currently empty or there is an ongoing half-speed transfer. If there is an ongoing low speed transfer, the system dynamically time shift or slows down the read rate out of the interleave buffer to half speed, and utilizes the free half of the bandwidth. This dynamic “zippering” or time shifting of data prevents a pipe pass from being rejected because the whole data bus is unavailable.
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Drapala Garrett M.
Dunn Deanna P.
Fee Michael
Augspurger Lynn L.
International Business Machines - Corporation
McConnell Dan E.
Shin Christopher B
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