Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-11-13
2010-11-16
Peugh, Brian R (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S159000, C345S557000
Reexamination Certificate
active
07836258
ABSTRACT:
According to embodiments of the invention, a distributed time base signal may be coupled to a memory directory which provides address translation for data located within a memory cache. The memory directory may have attribute bits which indicate whether or not the memory entries have been accessed by the distributed time base signal. Furthermore, the memory directory may have attribute bits which indicate whether or not a memory directory entry should be considered invalid after an access to the memory entry by the distributed time base signal. If the memory directory entry has been accessed by the distributed time base signal and the memory directory entry should be considered invalid after the access by the time base signal, any attempted address translation using the memory directory entry may cause a cache miss. The cache miss may initiate the retrieval of valid data from memory.
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Lee et al., Using cache Mechanisms to Exploit Nonrefreshing DRAM's for On-Chip Memories, Apr. 1991, IEEE Journal of Solid-State Circuits, vol. 26 No. 4, pp. 657-661.
Brown Jeffrey Douglas
Hoover Russell Dean
Mejdrich Eric Oliver
International Business Machines - Corporation
Patterson & Sheridan LLP
Peugh Brian R
Rutz Jared I
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