Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Patent
1993-12-14
1995-03-21
Hudspeth, David R.
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
326 21, H03K 19017
Patent
active
053999215
ABSTRACT:
A dynamic logic circuit style, which may be employed in fast logic circuits, is disclosed. The logic functionality is obtained using complementary pass transistor logic networks. Intermediate nodes and the complementary outputs are precharged to a high level during the precharge clock phase. During the evaluation clock phase, the inputs connected to gates of the pass transistors are constrained to either make a low-to-high transition or to maintain their initial low level; such signals are referred to as rising signals. The inputs connected to current electrodes of the pass transistors are constrained to either make a high-to-low transition or maintain their initial high level; such signals are referred to as falling signals. All signals are organized in pairs of true and complementary signals. In a falling signal pair, only one of the signals is allowed to make a high-to-low transition during an evaluation phase, while the other signal remains at the initial high level. In a rising signal pair, only one of the signals is allowed to make a low-to-high transition during an evaluation phase, while the other signal remains at the initial low level. This ensures that one of the true and complementary output nodes of the pass transistor networks makes a high-to-low transition, while the other node remains at a high level. The high-to-low transition is locally buffered by a clocked regenerative feedback circuit present on both output nodes. The signals on the output nodes form a pair of true and complementary signals which may be used as falling input signals for another circuit stage in the same circuit style. In the regenerative feedback circuits, the inverted output signals are produced and these signals form a pair of true and complementary rising signals which may be used as rising input signals for another circuit stage in the same circuit style.
REFERENCES:
patent: 4569032 (1986-02-01), Lee
patent: 4570084 (1986-07-01), Griffin
patent: 4692637 (1987-09-01), Shoji
patent: 4700086 (1987-10-01), Ling et al.
patent: 4710650 (1987-12-01), Shoji
patent: 4841174 (1989-06-01), Chung et al.
patent: 5015882 (1991-05-01), Houston et al.
patent: 5208490 (1993-05-01), Yetter
Yano, K. et al., "A 3.8-ns CMOS 16.times.16-b Multiplier . . . ", IEEE Journal of Solid-State Circuits, vol. 25, No. 2, Apr. 1990, pp. 388-395.
Krambeck, R. H. et al., "High-Speed Compact Circuits with CMOS", IEEE Journal of Solid State Circ., vol. SC-17, No. 3, Jun. 1982, pp. 614-619.
Glasser, L. A. and Dobber Puhl, D. W., "The Design and Analysis of VLSI Circuits", Addison-Wesley, 1985, p. 420, FIG. 8.5.
Childs, L. F.and Hirose, R. T., "An 18 ns 4K.times.4 CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, Oct. 1984, p. 548, FIG. 8.
Suzuki, M. et al., "A 1.5 ns 32b CMOS Alu in Double Pass-Transistor Logic", IEEE Int. Solid-State Circ. Conf. Digest, Feb. 1993, pp. 90-91.
Partovi, H. et al., "A Regenerative Push-Pull Differential Logic Family", IEEE Int. Solid-State Cir. Conf. Digest, Feb. 1994, pp. 294-295.
Heikes, C., "A 4.5 mm.sup.2 Multiplier Array for a 200 MFLOP Pipelined Coprocessor", IEEE Int. Solid-State Circ. Conf. Digest, Feb. 1994, pp. 290-291.
Hwang I. S. et al., "Ultrafast Compact 32-Bit CMOS Adders in Multiple-Output Domino Logic", IEEE Journ. Sol. State Circ., vol. 29, No. 2, Apr. 1989, pp. 358-369.
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