Dynamic CMOS logic circuit with precharge

Details Dynamic CMOS logic circuit with precharge Dynamic CMOS logic circuit with precharge

1993-09-14

1996-04-16

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 97, 326122, H03K 19017, H03K 190948

Patent

active

055086403

ABSTRACT:
A first transistor is connected to a second transistor so that the first and second transistors may be initially biased in a non-conducting state when a first node is at a first voltage potential and a second node is at a second voltage potential. A potential altering circuit selectively alters the voltage potential at the first and second nodes, causes the first and second transistors to be in a conducting state for accelerating a voltage transistion at the first and second nodes toward final values, and maintains the first and second nodes at their final voltage potentials for implementing a desired Boolean function.

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patent: 4575648 (1986-03-01), Lee
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patent: 4779010 (1988-10-01), Moss
patent: 4883989 (1989-11-01), Mizukami
patent: 4899066 (1990-02-01), Aikawa et al.
patent: 5153451 (1992-10-01), Yamamura et al.

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