Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-12-18
2004-03-23
Le, Don (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S023000, C326S121000
Reexamination Certificate
active
06710627
ABSTRACT:
TECHNICAL FIELD
This subject matter relates generally to dynamic circuits and, more particularly, to noise immunity of dynamic circuits.
BACKGROUND
Dynamic logic circuits are well-known in the semiconductor data processing art. Basically, dynamic circuits require a two-phase operation. In a first phase, an output of a dynamic circuit is precharged, and in a second phase the output of the dynamic circuit is evaluated. While such dynamic circuits provide quick operation with lower power consumption than their static counterparts, dynamic circuits are particularly susceptible to noise in an input signal. Such noise can include ground bounce, crosstalk, charge sharing, process variations, charge leakage, alpha particles, electro-magnetic radiation or other such unwanted electrical signals which occur within the circuit, resulting in spurious signals occurring at an output of a dynamic circuit. With dynamic circuits, in particular, such noise in an input signal may cause a precharged node therein to discharge, and an erroneous output signal will be produced when the noise rises above the threshold voltage of the transistors in the dynamic circuit.
As power supply voltages (V
cc
) are scaled down, the transistor threshold voltages (V
th
) also need to be reduced in order to preserve circuit performance. Generally, the trade-off for low-voltage circuits is between noise margins and performance. Also, generally the noise margin of dynamic circuits is directly related to V
th
, and a reduction in threshold values results in a reduced noise margin, and this reduction in noise margin may not be acceptable. Present solutions to the noise problems in dynamic circuits fall generally into two classes, the first being increasing noise margins of all inputs in the same way, and the second being independently controlling noise margins of each individual input. Increasing the noise margin of all inputs can result in reduced performance, when only some of the inputs are noisy. Whereas independently controlling the noise margins of each input is generally a good trade-off for low voltage circuits in terms of performance, the present techniques for independently controlling the noise margins of each input are generally applicable to only special type of circuits such as AND gates (dynamic circuits including series pull-down network).
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the data processing art for independently controlling the noise margins of each input in a dynamic circuit. This is especially needed in a dynamic circuit including a parallel or series-parallel pull-down network (such as OR and ANDOR gates) which has improved noise immunity that is not dependent on the type of circuitry (such as AND, OR, and ANDOR gates), and can generally work on all types of dynamic circuits.
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De Vivek K.
Stan Mircea R.
Intel Corporation
Le Don
Schwegman Lundberg Woessner & Kluth P.A.
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