Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Patent
1994-12-16
1997-02-25
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
326 95, 326 96, 326121, H03K 1920
Patent
active
056062702
ABSTRACT:
A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith. During inactive states of the clock signal, the first N-MOSFET becomes reverse-biased by the output node discharge voltage, while during inactive states of the inverse clock signal, the second P-MOSFET becomes reverse-biased by the output node charge voltage, thereby virtually eliminating charge leakage to and from the output node, respectively.
REFERENCES:
patent: 4780626 (1988-10-01), Guerin
patent: 5208489 (1993-05-01), Houston
patent: 5258666 (1993-11-01), Furuki
patent: 5384493 (1995-01-01), Furuki
Mead et al., Intro to VLSI Systems, Oct. 1980, pp. 33-37.
Neil H. E. Weste and Kamran Eshraghian, "Principles of CMOS VLSI Design, A Systems Perspective", Second Edition, Addison-Wesley Publishing Company, 1993, pp. 298-302 and 308-311.
Saburo Muroga, "VLSI System Design, When and How to Design Very-Large-Scale Integrated Circuits", John Wiley & Sons, 1982, pp. 221-224.
Yasuhiko Tsukikawa, Takeshi Kajimoto, Yasuhiko Okasaka, Yoshikazu Morooka, Kiyohiro Furutani, Hiroshi Miyamoto and Hideyuki Ozaki, "An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAM's", IEEE Journal of Solid-State Circuits, vol. 29, No. 4, Apr. 1994, pp. 534-538.
Ingemar Karlsson, "True Single Phase Clock Dynamic CMOS Circuit Technique", 1988 IEEE, pp. 475-478.
Yuan Ji-Ren, Ingemar Karlsson and Christer Svensson, "A True Single-Phase-Clock Dynamic CMOS Circuit Technique", IEEE Journal of Solid-State Circuits vol. SC-22, No. 5, Oct. 1987, pp. 899-901.
Jiren Yuan, Christer Svensson, "High-Speed CMOS Circuit Technique", IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, pp. 62.
Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi and Masakazu Aoki, "Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAM's", IEEE Journal of Solid-State Circuits, vol. 29, No. 7, Jul. 1994, pp. 761-769.
Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi and Masakazu Aoki, "Two-Dimensional Power-Line Selection Scheme for Low Subthreshold-Current Multi-Gigabit DRAM's" IEEE Journal of Solid-State Circuits, vol. 29, No. 8, Aug. 1994, pp. 887-894.
Takayuki Kawahara, Masashi Horiguchi, Yoshiki Kawajiri, Goro Kitsukawa, Tokuo Kure and Masakazu Aoki, "Subthreshold Current Reduction for Decoded-Driver by Self-Reverse Biasing", IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993, pp. 1136-1144.
Burr James B.
D'Souza Godfrey P.
Laird Douglas A.
Testa James F.
Sanders Andrew
Sun Microsystems Inc.
Westin Edward P.
LandOfFree
Dynamic clocked inverter latch with reduced charge leakage does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic clocked inverter latch with reduced charge leakage, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic clocked inverter latch with reduced charge leakage will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1976574