Dynamic clock mode switch

Details Dynamic clock mode switch Dynamic clock mode switch

1995-07-26

1996-11-26

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327156, 331DIG2, H03D 324

Patent

active

055793533

ABSTRACT:
A dynamic clock mode switch (11) is provided for switching clock frequencies while allowing continuing operation of a depending system. The switch includes an enable circuit for transmitting an enable signal, a phase-locked loop circuit (PLL) (15) for locking onto an input clock frequency in response to said enable circuit, a PLL lock indicator for receiving a PLL lock signal (29) from said PLL, and a clock multiplexer with a multiplier for multiplying said input clock frequency by a predetermined factor in response to said enable circuit and PLL clock signals.

REFERENCES:
patent: 3887941 (1975-06-01), Dann et al.
patent: 5184350 (1993-02-01), Dara
patent: 5258720 (1993-11-01), Tanis et al.
patent: 5260979 (1993-11-01), Parker et al.
patent: 5331667 (1994-07-01), Izumi

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