Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data... – Inhibiting timing generator or component
Reexamination Certificate
1998-12-30
2001-02-06
Heckler, Thomas M. (Department: 2787)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
Inhibiting timing generator or component
Reexamination Certificate
active
06185694
ABSTRACT:
FIELD
The present invention relates to dynamic clock distribution.
BACKGROUND
There exists a continuing need for an arrangement effecting selective enabling/disabling of an existing functional block and an expansion functional block within a system (e.g., on a motherboard), while reducing the liklihood of malfunctioning or degrading (e.g., overloading) of a system clock. Considering a graphics controller functional block as an example, some resellers of computer systems desire to provide their customers with a selection of graphics capabilities, and thus desire to provide computer systems capable of being fitted with different graphics controllers. However, manufacturers generally desire to provide a generic graphics controller as standard equipment, while leaving it to the resellers to add a customized one at the time of sale of the system, if desired. In addition, some users of computer systems may at some time after the purchase decide to upgrade or change the graphics controller by inserting one in an expansion slot on the computer. Having two graphics controllers coupled to the computer system clock circuit at the same time might create an undesirable clock circuit load, and might cause edge rate degradation of the clock signals.
In the past, a dual in-line package (DIP) switch, a jumper, or other hardware on the motherboard was used to activate the add-on graphics controller, while disabling the built-in one. This is a cumbersome process employing tedious intervention by the user, in contrast to easier “plug-and-play” additions to the computer system.
SUMMARY
The present invention is an arrangement for dynamic clock distribution with respect to functional blocks. A clock control circuit includes a source of a select signal for selecting between operation of a first functional block and a second functional block. A clock steering circuit receives clock signals from a clock signal source and in response to a first predetermined state of the select signal prevents clock signals from being applied to the first functional block while enabling clock signals to be applied to the second functional block. In response to a second predetermined state of the select signal, the clock steering circuit enables clock signals to be applied to the first functional block while preventing clock signals from being applied to the second functional block.
REFERENCES:
patent: 5450574 (1995-09-01), Madter et al.
patent: 5511209 (1996-04-01), Mensch, Jr.
patent: 5630143 (1997-05-01), Maher et al.
patent: 5754837 (1998-05-01), Walsh et al.
patent: 6055644 (2000-04-01), Henkel
Antonelli Terry Stout & Kraus LLP
Heckler Thomas M.
Intel Corp.
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