Dynamic clock control circuit and method

Details Dynamic clock control circuit and method Dynamic clock control circuit and method

2004-07-29

2010-11-02

Lee, Thomas (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S320000, C713S600000

Reexamination Certificate

active

07827424

ABSTRACT:
A variable clock control information generator receives vertical blank interval information corresponding to a vertical blank interval (VBI) during display rasterization. The vertical blank interval is a period of time in a video display signal that temporarily suspends transmission of video data as is known during display rasterization, to allow a display to return back up to (retrace) the first line of the display after scanning the end of the display. In response to the received vertical blank interval information, the variable clock control information generator produces memory clock control information to change the frequency of a memory clock divider signal during the detected vertical blank interval.

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JEDEC Solid State Technology Associate; JEDEC Standard; DD42 SDRAM Specification; Jan. 2004; JEDEC Solid State Technology Association; Arlington, VA.

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