Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2007-09-04
2007-09-04
Le, Don (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S038000
Reexamination Certificate
active
11205668
ABSTRACT:
A clock change circuit includes enabling a clock change frequency to be accepted while a system is active and clock frequencies are at a low period. The circuit includes generating an enabling signal representing a window of time in which a frequency change is accomplished.
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Shi, Kaijian et al, Hierarchical Timing Closure Methodology for OMAP: An Open Multimedia Application Platform, ASIC, 2003.vol. 1, pp. 238-241, (no month).
Chang Christopher
Parker Jeffrey Lewis
Digi International Inc.
Greenberg & Traurig, LLP
Kozik Kenneth F.
Le Don
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