Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2003-01-07
2004-07-06
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S119000
Reexamination Certificate
active
06759877
ABSTRACT:
BACKGROUND OF INVENTION
A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system.
FIG. 1
shows a typical computer system (
10
) having: a microprocessor (
12
), memory (
14
), integrated circuits (
16
) that have various functionalities, communication paths (
18
), i.e., buses and wires, that transfer data among the aforementioned components of the computer system (
10
), and a clock (
20
) that is used to synchronize operations of the computer system (
10
).
The various computations and operations performed by the computer system are facilitated through the use of signals that provide electrical pathways for data to propagate between the various components of the computer system. In a general sense, the passing of data onto a signal may be accomplished by changing, i.e., transitioning, the logical value, i.e., the logical state, of the signal. Specifically, the logical state of a signal may be transitioned by either raising the voltage of the signal or reducing the voltage of the signal. When the voltage is raised, the signal is said to be at a “logic high,” and when the voltage is reduced, the signal is said to be at a “logic low.”
A microprocessor (
12
), such as the one shown in
FIG. 1
, includes various IC computational blocks, e.g., arithmetic logic units, that store, transfer, and manipulate logic signals in order to perform arithmetic and logic operations. In order to maximize performance, IC computational blocks are typically fabricated using synchronous logic components, i.e., logic components whose operations may be synchronized to the logical transitions of a particular signal (such as a clock signal generated by the clock (
20
)). One example of a synchronous logic component is a dynamic circuit, i.e., a logic circuit that, given a particular input combination, outputs a constant value for the input combination for a specified period of time. Thus, given its time-dependent nature, the dynamic circuit may be used to output the constant value for specified logical transitions of the clock signal.
A typical dynamic circuit is shown in FIG.
2
. Note that, typically, dynamic circuits generate output values for logic operations such as AND, NAND, OR, and NOR. In particular, the dynamic circuit of
FIG. 2
generates an output value for a logical OR operation. The dynamic circuit shown includes the following circuitry: a first set of input devices (
22
), a second set of input devices (
24
), a first dynamic node (
26
), a second dynamic node (
28
), a first precharge device (
30
), a second precharge device (
32
), a first keeper device (
36
), a second keeper device (
38
), and a NAND gate (
34
). In addition to the abovementioned circuitry, the dynamic circuit includes a clock signal input clk that is input to the first and second precharge devices (
30
,
32
) and an output signal out that is output by the NAND gate (
34
).
In general, the operation of the dynamic circuit may be broken into a precharge phase and an evaluation phase. In the dynamic circuit shown in
FIG. 2
, the precharge phase occurs when clk is ‘low,’ and the evaluation phase occurs when clk is ‘high.’ In the precharge phase, the dynamic circuit is readied for the evaluation phase by the signal to which the dynamic circuit is synchronized, i.e., clk. In particular, when clk transitions ‘low,’ the first and second precharge devices (
30
,
32
) turn ‘on’ and respectively force the values of the dynamic nodes (
26
,
28
) to ‘high.’ In turn, the NAND gate (
34
) forces the value of the output signal out to ‘low.’
Then, in the evaluation phase, the logical OR operation represented by the dynamic circuit is evaluated. In particular, when clk transitions ‘high,’ the first and second precharge devices (
30
,
32
) turn ‘off,’ and the values of the first and second dynamic nodes (
26
,
28
) are respectively controlled by the first and second sets of input devices (
22
,
24
). Thus, if either the input value generated by the first set of input devices (
22
) or the input value generated by the second set of input devices (
24
) transitions ‘low,’ then out is forced ‘high.’ However, if the input values of both the first and second sets of transistors (
22
,
24
) remain ‘low,’ then out remains ‘low.’
The input values generated by the first and second sets of input devices (
22
,
24
) are determined as follows. In
FIG. 2
, the first set of input devices (
22
) and the second set of input devices (
24
) are both composed of n-type transistors whose states are dependent on logical values input to the dynamic circuit. As shown, the n-type transistors are arranged into transistor pairs, i.e., pull-downs, that represent AND functions. Thus, during the evaluation phase, one of two things may happen in either one or both sets of input devices. First, in a single set of input devices, if the one or more of the pull-downs switch ‘on,’ the corresponding dynamic node is connected to ground, i.e., the value of the dynamic node is driven ‘low.’ On the other hand, if, in a single set of input devices, none of the pull-downs switch ‘on,’ the corresponding dynamic node remains disconnected from ground, i.e., the value of the dynamic node remains ‘high.’
Note that, in the dynamic circuit, the first and second keeper devices (
36
,
38
) are used to prevent current leakage from the first and second sets of input devices (
22
,
24
). Specifically, during the evaluation phase, sub-threshold leakage current may flow through some or all of the pull-downs even when the pull-downs are ‘off.’ As a result, the voltage on the internal dynamic node may fall, resulting in erroneous evaluation. Thus, to ensure that, during the evaluation phase, current leakage from a pull-down does not discharge the first and/or second dynamic nodes (
22
,
24
), the first and second keeper devices (
36
,
38
) are turned ‘on’ by out to increase an amount of pull-up current flowing through the first and second dynamic nodes (
22
,
24
).
Note that, for a typical dynamic circuit such as shown in
FIG. 2
, the strengths, i.e., sizes, of keeper devices are determined during a design phase of the dynamic circuit. In particular, keeper devices are sized based on a worst case leakage corner simulated for the dynamic circuit (i.e., greater current leakage typically requires larger keeper devices). However, during the evaluation phase, an amount of offset current generated by keeper devices, especially large keeper devices, often negatively impacts speed and/or functionality of the pull-downs included in the sets of input devices. Thus, keeper devices cannot be made arbitrarily large without degrading the dynamic circuit's performance.
In many cases, this fundamental tradeoff between keeper device strength and evaluation performance imposes a limit on a number of pull-downs that may be included in a particular set of input devices used to control a particular dynamic node. Increasing the number of evaluation devices in a dynamic circuit typically increases the amount of leakage current proportionally. Therefore larger keeper devices are required. However, at some point, the size of the keeper device becomes so large that a single evaluation transistor is unable to overcome the keeper device's size and pull the dynamic node low. As a result, an upper limit is enforced on a number of input values that may be used for the particular arithmetic and/or logical computation performed by a dynamic circuit or by a computational block that incorporates a dynamic circuit.
SUMMARY OF INVENTION
According to one aspect of the invention, an integrated circuit comprises a temperature sensor arranged to -generate a temperature signal dependent on a temperature of the integrated circuit; and a dynamic logic circuit, comprising: a first dynamic node and a first keeper stage operatively connected to the first dynamic node and arranged to receive the t
Desai Shaishav A.
Gauthier Claude R.
Mehta Anup S.
Nguyen Linh V
Osha & May L.L.P.
Sun Microsystems Inc.
Tokar Michael
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