Dynamic circuit having improved noise immunity and method theref

Details Dynamic circuit having improved noise immunity and method theref Dynamic circuit having improved noise immunity and method theref

1996-12-17

1998-10-06

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 83, H03K 19096

Patent

active

058182640

ABSTRACT:
A dynamic circuit has an improved noise margin that is not solely dominated by a threshold voltage of the transistors from which it is comprised. A transistor is utilized such that a ratio of the width of the feedback device to a pull-down transistor in a dynamic circuit determines when the pull-down transistor becomes active and conducts current. Therefore, rather than having a low threshold voltage which may be significantly and substantially impacted by the presence of noise on an input signal, beta ratioed transistors are implemented to give greater noise immunity and increase a circuit's ability to tolerate noisy input lines. Furthermore, a structure of the dynamic circuit of the dynamic circuit preserves the functionality of that circuit. More specifically, after a dynamic node of a circuit of the present invention has been discharged, the node remains discharged and is only precharged again when a subsequent clock pulse occurs.

REFERENCES:
patent: 4825106 (1989-04-01), Tipon et al.
patent: 4866307 (1989-09-01), Ashmore, Jr.
patent: 4958088 (1990-09-01), Farah-Bakhsh et al.
patent: 5117133 (1992-05-01), Luebs
patent: 5151616 (1992-09-01), Komuro
patent: 5151622 (1992-09-01), Thrower et al.
patent: 5194767 (1993-03-01), Chao
patent: 5465054 (1995-11-01), Erhart
patent: 5650733 (1997-07-01), Covino
U.S. Patent Application Serial No., entitled "Dynamic CMOS Circuits with Noise Immunity" (Attorney Docket No. BU9-95-066).

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