Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2005-11-22
2005-11-22
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S096000, C326S098000
Reexamination Certificate
active
06967502
ABSTRACT:
In a dynamic circuit, when only between a precharge node and an intermediate node through a plurality of logical-operating MOS transistors is conducted, the potential of the precharge node approximately drops to High*{C1/(C1+C2)} from High, where C1represents the capacitance of the precharge node and C2represents the capacitance of the intermediate node. Thereafter, with the charge from a power supply, the precharge node returns to High. At this charge sharing time, the amount of charge supply from the power supply is adjusted to suppress voltage drop of the precharge node, thereby reducing noise.
REFERENCES:
patent: 6002271 (1999-12-01), Chu et al.
patent: 6002292 (1999-12-01), Allen et al.
patent: 6097207 (2000-08-01), Bernstein et al.
patent: 6184718 (2001-02-01), Tran et al.
patent: 6326814 (2001-12-01), Stasiak et al.
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Tran Anh Q.
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