Dynamic cache coherency snooper presence with variable snoop...

Details Dynamic cache coherency snooper presence with variable snoop... Dynamic cache coherency snooper presence with variable snoop...

2006-01-10

2006-01-10

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S305000, C711S146000

Reexamination Certificate

active

06985972

ABSTRACT:
A data processing system with a snooper that is capable of dynamically enabling and disabling its snooping capabilities (i.e., snoop detect and response). The snooper is connected to a bus controller via a plurality of interconnects, including a snooperPresent signal, a snoop response signal and a snoop detect signal. When the snooperPresent signal is asserted, subsequent snoop requests are sent to the snooper, and the snooper is polled for a snoop response. Each snooper is capable of responding at different times (i.e., each snooper operates with different snoop latencies). The bus controller individually tracks the snoop response received from each snooper with the snooperPresent signal enabled. Whenever the snooper wishes to deactivate its snooping capabilities/operations, the snooper de-asserts the snooperPresent signal. The bus controller recognizes this as an indication that the snooper is unavailable. Thus, when the bus controller broadcasts subsequent snoop requests, the bus controller does not send the snoop request to the snooper.

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The CoreConnect Bus Architecture, IBM, 1999.

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