Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-05-14
2001-02-06
Etienne, Ario (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S115000, C710S116000, C710S122000, C710S123000, C710S243000
Reexamination Certificate
active
06185647
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a bus control apparatus for use in information processing apparatus such as a personal computer, a work station, an office computer, etc., and more particularly to a bus control apparatus for optimizing the connection positions of slots through which devices are connected to a bus.
2. Description of the Related Art
Recent information processing apparatus tends to include more and more devices in the form of peripheral units such as a storage unit and an input/output unit to be connected to buses, due to the increase in type of the devices. However, the number of devices connectable to a single bus is electrically restricted, so that the bus is divided so as to have a hierarchical structure. More specifically, an upper hierarchical device bus is connected via a host bridge to a host bus connecting to a host, with a lower hierarchical device bus being connected via a bus bridge to the upper hierarchical device bus, to thereby constitute a hierarchical bus allowing the devices such as the storage unit, the input/output unit, etc., to be connected to a plurality of slots provided on the upper and lower hierarchical buses. In the case of such a conventional hierarchical bus, the positions of the slots for connecting the peripheral units to the respective hierarchical buses are fixedly mapped. For this reason, in the case where the host accesses a device connected to a slot on the lower hierarchical bus, processing time will be elongated since the access is effected from the upper hierarchical bus through the bus bridge to the lower hierarchical bus. Thus, in the case of structuring a hierarchical bus, the devices are fixedly mapped taking into consideration the upper hierarchical bus having a short access time and the lower hierarchical bus having a long access time. However, the states of the access to the devices vary depending on the applications executed by the host. Some processing may incur a concentration of accesses to the device mapped to the lower hierarchical bus, with the result that elongation of the access time may possibly lead to a low processing performance.
On the contrary, even in the case of an ordinary bus having no hierarchical structure, an electrical characteristic, for instance, a delay time of the access from the host differs depending on the positions of connections of the slots to the bus. As a result of this, a plurality of devices connected to the same bus also have different access time depending on their bus connecting positions. For this reason, in case accesses are concentrated to the device connected to the position having an insufficient electrical characteristic, the access time may be increased or an error attributable to an electrical fault may occur, which requires a retry for recovery, resulting in a lower processing performance as a whole.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a bus control apparatus for adding to the speed of transfer on a bus having a hierarchical structure.
The present invention is directed to a bus control apparatus for a hierarchical bus, comprising a hierarchical bus connected to a host apparatus and consisting at least of an upper hierarchical bus and a lower hierarchical bus, a plurality of slots selectively connectable to the hierarchical bus in order to connect a device receiving an input/output demand from the host apparatus; a priority decision circuit for deciding priorities of the plurality of slots; and a bus mapping circuit for connecting each of the plurality of slots to the hierarchical bus to allow an execution of processing in response to an access demand from the host apparatus on the basis of the priorities determined by the priority decision circuit. In this case, the priority decision circuit decides the priorities on the basis of the frequencies of access of the host apparatus to devices connected to the plurality of slots. That is, the bus mapping circuit has an access counter which counts up the number of times of access of the host apparatus to the devices connected to the plurality of slots at a specified interval, and the priority decision circuit sets priorities of the slots in descending order of access number of times counted up by the access counter. At the start of use of the apparatus by the power on, the priority decision circuit assigns previously defined priorities to the plurality of slots whereas in use it assigns the priorities to the slots in descending order of the number of times of access of the host apparatus to the devices connected to the plurality of slots which are counted up by the access counter at a specified interval. Furthermore, the bus mapping circuit allows a non-volatile memory unit to store at the time of power off the priorities of the plurality of slots determined by the priority decision circuit, and the bus mapping circuit reads out the priorities stored in the non-volatile memory unit at the start of use by the next power on, to thereby perform initialization. When the priority decision circuit recognizes an unused slot which is not connected to the device among said plurality of slots, it assigns the lowest priority to said unused slot. The bus mapping circuit performs mapping allowing a slot having a higher priority to be connected to the upper hierarchical bus whereas it performs mapping allowing a slot having a lower priority to be connected to the lower hierarchical bus. According to such a bus control apparatus of the present invention, in case the upper hierarchical bus includes any slots having no access from the upper hierarchical bus and the lower hierarchical bus includes any slots having frequent accesses from the lower hierarchical bus, the bus connection is again mapped so that more frequently accessed lower hierarchical bus slot is turned to the upper hierarchical bus, thereby eliminating the access via the bus bridge to shorten the access path, making it possible to add to the bus access speed.
It is another object of the present invention to provide a bus control apparatus for increasing the speed of transfer on an ordinary bus having no hierarchical structure. This bus control apparatus comprises a bus connected to a host apparatus; a plurality of slots selectively connectable to buses for connecting devices receiving an input/output demand from the host apparatus; a plurality of slot connection positions provided on the buses for connecting a plurality of slots having priorities set in the descending order of the electrical characteristics with the host apparatus; a priority decision circuit for determining the priorities of the plurality of slots; and a bus mapping circuit for connecting each of the plurality of slots to the slot connection positions on the buses on the basis of the priorities determined by the priority decision circuit to thereby allow the execution of processing in response to the access demand from the host apparatus. The detail of the priority decision circuit in this case is the same as that of the case using the hierarchical bus and is provided with the access counter and the non-volatile memory. The bus mapping circuit performs mapping allowing a slot having a higher priority to be connected to a slot connection point having a higher priority whereas it performs mapping allowing a slot having a lower priority to be connected to a slot connection point having a lower priority. According to the bus control apparatus of the present invention, in case a frequently accessed slot lies in a bus connection position having a relatively low electric characteristic, the frequently accessed slot is again mapped to another slot connection position on the bus having a superior bus electric characteristic, so that the electric characteristic is improved to for instance shorten the delay time, making it possible to increase the bus access speed.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description with ref
Etienne Ario
Fujitsu Limited
Staas & Halsey , LLP
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