Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1998-06-03
2000-12-05
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711158, 710 57, 710116, 709107, G06F 1200
Patent
active
061579890
ABSTRACT:
An arbitration and task switching technique in a real-time multiprocessor data processing system (20) having a common bus (32) and a segmented shared memory (30), where fullness of memory segments of the shared memory (30) is used as a measurement for arbitration and task switching priorities. A bus request mechanism in each of the processors dynamically calculates normalized priority values based on relative needs across the system (20). The normalized priority calculation is based on monitoring the fullness of memory segments of the shared memory (30) associated with each processor (24, 26, 28) of the system (20). Using this normalized priority calculation, the bus access order and bus bandwidth are optimally allocated according to tasks executed by the processors (24, 26, 28). Also, the normalized priority calculation and a preprogrammed threshold is used to control task switching in the multi-processor system (20).
REFERENCES:
patent: 5469558 (1995-11-01), Lieberman et al.
patent: 5524235 (1996-06-01), Larson et al.
patent: 5983303 (1999-11-01), Sheafor et al.
Collins Eric S.
Hill Reginald J.
Lindsley Brett L.
Anderson Matthew D.
Cabeca John W.
Hill Daniel D.
Motorola Inc.
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