Dynamic bus

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates

Patent

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Details

326 95, 326 83, 326112, H03K 1900, H03K 19096

Patent

active

060669640

ABSTRACT:
A bi-phase, single-wire dynamic bus for allowing communication during either of a first phase or a second phase of a clock signal is presented. A data signal that is to be written onto a single bus wire is written onto the bus, via a write enable circuit, during one of the first or second clock phase. A precharger circuit precharges the bus on the subsequent clock phase, which is the other of the first or second clock phase.

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