Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-08-08
2006-08-08
Bataille, Pierre (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
07089356
ABSTRACT:
A method is described for parallel processing of sequence operations, in which contention for the sequence operation is reduced among multiple parallel processes. Contention is reduced by caching sequence values locally for each parallel process. Each process accesses the sequence operation, or an instance level cache of sequence values, in a batched manner, thereby returning a block of unique sequence values instead of a single sequence value. The block of sequence values, or at least information that indicates a range of sequence values that define the block, is then cached locally in association with a given process of the multiple processes. Hence, future requests for sequence values from the given process are serviced from the local cache, rather than having to access the sequence operation and risk contention for the operation with other processes.
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Chen Rushan
Ghosh Bhaskar
Bataille Pierre
Henkhaus John D.
Hickman Palermo & Truong & Becker LLP
Oracle International Corporation
Schlie Paul
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